ID_DFR1_EL1, Debug Feature Register 1
The ID_DFR1_EL1 characteristics are:
Purpose
Provides top level information about the debug system in AArch32.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register ID_DFR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_DFR1[31:0] .
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
Attributes
ID_DFR1_EL1 is a 64-bit register.
Field descriptions
The ID_DFR1_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:4]
Reserved, RES0.
MTPMU, bits [3:0]
Multi-threaded PMU extension. Defined values are:
| MTPMU | Meaning |
|---|---|
| 0b0000 |
FEAT_MTPMU not implemented. If PMUv3 is implemented, it is IMPLEMENTATION DEFINED whether PMEVTYPER<n>_EL0.MT are read/write or RES0. |
| 0b0001 |
FEAT_MTPMU implemented and PMEVTYPER<n>_EL0.MT are read/write. When FEAT_MTPMU is disabled, the Effective values of PMEVTYPER<n>.MT are 0. |
| 0b1111 |
FEAT_MTPMU not implemented. If PMUv3 is implemented, PMEVTYPER<n>_EL0.MT are RES0. |
All other values are reserved.
FEAT_MTPMU implements the functionality identified by the value 0b0001.
In an Armv8.6-compliant implementation that includes PMUv3, the value 0b0000 is not permitted.
In an implementation that does not include PMUv3, the value 0b0001 is not permitted.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the ID_DFR1_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_DFR1_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0011 | 0b101 |
if PSTATE.EL == EL0 then
if IsFeatureImplemented("FEAT_IDST") then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (!IsZero(ID_DFR1_EL1) || boolean IMPLEMENTATION_DEFINED "ID_DFR1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_DFR1_EL1;
elsif PSTATE.EL == EL2 then
return ID_DFR1_EL1;
elsif PSTATE.EL == EL3 then
return ID_DFR1_EL1;