ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0
The ID_ISAR0_EL1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register ID_ISAR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR0[31:0] .
Attributes
ID_ISAR0_EL1 is a 64-bit register.
Field descriptions
The ID_ISAR0_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:28]
Reserved, RES0.
Divide, bits [27:24]
Indicates the implemented Divide instructions. Defined values are:
Divide | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds SDIV and UDIV in the T32 instruction set. |
0b0010 |
As for 0b0001, and adds SDIV and UDIV in the A32 instruction set. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Debug, bits [23:20]
Indicates the implemented Debug instructions. Defined values are:
Debug | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds BKPT. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Coproc, bits [19:16]
Indicates the implemented System register access instructions. Defined values are:
Coproc | Meaning |
---|---|
0b0000 |
None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions. |
0b0001 |
Adds generic CDP, LDC, MCR, MRC, and STC. |
0b0010 |
As for 0b0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2. |
0b0011 |
As for 0b0010, and adds generic MCRR and MRRC. |
0b0100 |
As for 0b0011, and adds generic MCRR2 and MRRC2. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
CmpBranch, bits [15:12]
Indicates the implemented combined Compare and Branch instructions in the T32 instruction set. Defined values are:
CmpBranch | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds CBNZ and CBZ. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
BitField, bits [11:8]
Indicates the implemented BitField instructions. Defined values are:
BitField | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds BFC, BFI, SBFX, and UBFX. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
BitCount, bits [7:4]
Indicates the implemented Bit Counting instructions. Defined values are:
BitCount | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds CLZ. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Swap, bits [3:0]
Indicates the implemented Swap instructions in the A32 instruction set. Defined values are:
Swap | Meaning |
---|---|
0b0000 |
None implemented. |
0b0001 |
Adds SWP and SWPB. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the ID_ISAR0_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_ISAR0_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_ISAR0_EL1; elsif PSTATE.EL == EL2 then return ID_ISAR0_EL1; elsif PSTATE.EL == EL3 then return ID_ISAR0_EL1;