ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2
The ID_MMFR2_EL1 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register ID_MMFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR2[31:0] .
Attributes
ID_MMFR2_EL1 is a 64-bit register.
Field descriptions
The ID_MMFR2_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:32]
Reserved, RES0.
HWAccFlg, bits [31:28]
Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:
HWAccFlg | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Support for VMSAv7 Access flag, updated in hardware. |
All other values are reserved.
From Armv8, the only permitted value is 0b0000.
WFIStall, bits [27:24]
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:
WFIStall | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Support for WFI stalling. |
All other values are reserved.
From Armv8, the permitted values are 0b0000 and 0b0001.
MemBarr, bits [23:20]
Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==0b1111) encoding space:
MemBarr | Meaning |
---|---|
0b0000 |
None supported. |
0b0001 |
Supported memory barrier System instructions are:
|
0b0010 |
As for 0b0001, and adds:
|
All other values are reserved.
From Armv8, the only permitted value is 0b0010.
Arm deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.
UniTLB, bits [19:16]
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:
UniTLB | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Supported unified TLB maintenance operations are:
|
0b0010 |
As for 0b0001, and adds:
|
0b0011 |
As for 0b0010, and adds:
|
0b0100 |
As for 0b0011, and adds:
|
0b0101 |
As for 0b0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH. |
0b0110 |
As for 0b0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0110.
HvdTLB, bits [15:12]
If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. Arm deprecates the use of this field by software.
L1HvdRng, bits [11:8]
Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:
L1HvdRng | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Supported Level 1 Harvard cache maintenance range operations are:
|
All other values are reserved.
From Armv8, the only permitted value is 0b0000.
L1HvdBG, bits [7:4]
Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:
L1HvdBG | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Supported Level 1 Harvard cache background fetch operations are:
|
All other values are reserved.
From Armv8, the only permitted value is 0b0000.
L1HvdFG, bits [3:0]
Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:
L1HvdFG | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Supported Level 1 Harvard cache foreground fetch operations are:
|
All other values are reserved.
From Armv8, the only permitted value is 0b0000.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the ID_MMFR2_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_MMFR2_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_MMFR2_EL1; elsif PSTATE.EL == EL2 then return ID_MMFR2_EL1; elsif PSTATE.EL == EL3 then return ID_MMFR2_EL1;