RVBAR_EL3, Reset Vector Base Address Register (if EL3 implemented)
The RVBAR_EL3 characteristics are:
Purpose
If EL3 is the highest Exception level implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch64 state.
Configuration
This register is present only when EL3 is implemented. Otherwise, direct accesses to RVBAR_EL3 are UNDEFINED.
Only implemented if the highest Exception level implemented is EL3.
Attributes
RVBAR_EL3 is a 64-bit register.
Field descriptions
The RVBAR_EL3 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Reset Address | |||||||||||||||||||||||||||||||
| Reset Address | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Reset Address. The IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 00, as this address must be aligned, and the address must be within the physical address size supported by the PE.
Accessing the RVBAR_EL3
Accesses to this register use the following encodings:
MRS <Xt>, RVBAR_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b1100 | 0b0000 | 0b001 |
if PSTATE.EL == EL3 && IsHighestEL(EL3) then
return RVBAR_EL3;
else
UNDEFINED;