SDER32_EL2, AArch32 Secure Debug Enable Register
The SDER32_EL2 characteristics are:
Purpose
Allows access to the AArch32 register SDER from Secure EL2 and EL3 only.
Configuration
This register is present only when EL2 is implemented, AArch32 is supported at any Exception level, FEAT_SEL2 is implemented and EL1 supports AArch32. Otherwise, direct accesses to SDER32_EL2 are UNDEFINED.
This register is ignored by the PE when one or more of the following are true:
-
The PE is in Non-secure state.
-
EL1 is using AArch64.
Attributes
SDER32_EL2 is a 64-bit register.
Field descriptions
The SDER32_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SUNIDEN | SUIDEN | |||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:2]
Reserved, RES0.
SUNIDEN, bit [1]
Secure User Non-Invasive Debug Enable.
| SUNIDEN | Meaning |
|---|---|
| 0b0 |
This bit does not affect Performance Monitors event counting at Secure EL0. |
| 0b1 |
If EL1 is using AArch32, Performance Monitors event counting is allowed in Secure EL0. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SUIDEN, bit [0]
Secure User Invasive Debug Enable.
| SUIDEN | Meaning |
|---|---|
| 0b0 |
This bit does not affect the generation of debug exceptions at Secure EL0. |
| 0b1 |
If EL1 is using AArch32, debug exceptions from Secure EL0 are enabled. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the SDER32_EL2
Accesses to this register use the following encodings:
MRS <Xt>, SDER32_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return SDER32_EL2;
elsif PSTATE.EL == EL3 then
return SDER32_EL2;
MSR SDER32_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
SDER32_EL2 = X[t];
elsif PSTATE.EL == EL3 then
SDER32_EL2 = X[t];