TRCIDR1, ID Register 1
The TRCIDR1 characteristics are:
Purpose
Returns the tracing capabilities of the trace unit.
Configuration
AArch64 System register TRCIDR1 bits [31:0] are architecturally mapped to External register TRCIDR1[31:0] .
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR1 are UNDEFINED.
Attributes
TRCIDR1 is a 64-bit register.
Field descriptions
The TRCIDR1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| DESIGNER | RES0 | RES1 | TRCARCHMAJ | TRCARCHMIN | REVISION | ||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
DESIGNER, bits [31:24]
Indicates which company designed the trace unit. The permitted values of this field are the same as MIDR_EL1.Implementer.
Bits [23:16]
Reserved, RES0.
Bits [15:12]
Reserved, RES1.
TRCARCHMAJ, bits [11:8]
Major architecture version.
| TRCARCHMAJ | Meaning |
|---|---|
| 0b1111 |
If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
TRCARCHMIN, bits [7:4]
Minor architecture version.
| TRCARCHMIN | Meaning |
|---|---|
| 0b1111 |
If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
REVISION, bits [3:0]
Implementation revision.
Returns an IMPLEMENTATION DEFINED value that identifies the revision of:
- The trace registers.
- The OS Lock registers.
Arm recommends that the initial implementation sets REVISION == 0x0 and the field then increments for any subsequent implementations. However, it is acceptable to omit some values or use another scheme to identify the revision number.
Arm recommends that TRCPIDR2.REVISION == TRCIDR1.REVISION. However, in situations where it is difficult to align these fields, such as with a metal layer fix then it is acceptable to change the REVISION fields independently.
Accessing the TRCIDR1
Accesses to this register use the following encodings:
MRS <Xt>, TRCIDR1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b1001 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR1;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR1;
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR1;