TRCIMSPEC0, IMP DEF Register 0
The TRCIMSPEC0 characteristics are:
Purpose
TRCIMSPEC0 shows the presence of any IMPLEMENTATION DEFINED features, and provides an interface to enable the features that are provided.
Configuration
AArch64 System register TRCIMSPEC0 bits [31:0] are architecturally mapped to External register TRCIMSPEC0[31:0] .
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIMSPEC0 are UNDEFINED.
Attributes
TRCIMSPEC0 is a 64-bit register.
Field descriptions
The TRCIMSPEC0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EN | SUPPORT | |||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:8]
Reserved, RES0.
EN, bits [7:4]
When TRCIMSPEC0.SUPPORT != 0b0000:
When TRCIMSPEC0.SUPPORT != 0b0000:
Enable. Controls whether the IMPLEMENTATION DEFINED features are enabled.
| EN | Meaning |
|---|---|
| 0b0000 |
The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION DEFINED features are not supported. |
| 0b0001 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0010 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0011 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0100 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0101 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0110 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b0111 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1000 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1001 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1010 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1011 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1100 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1101 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1110 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
| 0b1111 |
The trace unit behavior is IMPLEMENTATION DEFINED. |
On a Trace unit reset, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
SUPPORT, bits [3:0]
Indicates whether the implementation supports IMPLEMENTATION DEFINED features.
| SUPPORT | Meaning |
|---|---|
| 0b0000 |
No IMPLEMENTATION DEFINED features are supported. |
| 0b0001 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0010 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0011 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0100 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0101 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0110 |
IMPLEMENTATION DEFINED features are supported. |
| 0b0111 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1000 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1001 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1010 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1011 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1100 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1101 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1110 |
IMPLEMENTATION DEFINED features are supported. |
| 0b1111 |
IMPLEMENTATION DEFINED features are supported. |
Use of nonzero values requires written permission from Arm.
Access to this field is RO.
Accessing the TRCIMSPEC0
Accesses to this register use the following encodings:
MRS <Xt>, TRCIMSPEC0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b0000 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCIMSPECn == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIMSPEC0;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIMSPEC0;
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIMSPEC0;
MSR TRCIMSPEC0, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b0000 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRCIMSPECn == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCIMSPEC0 = X[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCIMSPEC0 = X[t];
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCIMSPEC0 = X[t];