AMCGCR, Activity Monitors Counter Group Configuration Register
The AMCGCR characteristics are:
Purpose
Provides information on the number of activity monitor event counters implemented within each counter group.
Configuration
External register AMCGCR bits [31:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[31:0] .
External register AMCGCR bits [31:0] are architecturally mapped to AArch32 System register AMCGCR[31:0] .
The power domain of AMCGCR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCGCR are RES0.
Attributes
AMCGCR is a 32-bit register.
Field descriptions
The AMCGCR bit assignments are:
Bits [31:16]
Reserved, RES0.
CG1NC, bits [15:8]
Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.
In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.
CG0NC, bits [7:0]
Counter Group 0 Number of Counters. The number of counters in the architected counter group.
In an implementation that includes FEAT_AMUv1, the value of this field is 4.
Accessing the AMCGCR
AMCGCR can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
AMU | 0xCE0 | AMCGCR |
Accesses on this interface are RO.