AMCNTENCLR1, Activity Monitors Count Enable Clear Register 1
The AMCNTENCLR1 characteristics are:
Purpose
Disable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>.
Configuration
External register AMCNTENCLR1 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR1_EL0[31:0] .
External register AMCNTENCLR1 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR1[31:0] .
The power domain of AMCNTENCLR1 is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENCLR1 are RES0.
Attributes
AMCNTENCLR1 is a 32-bit register.
Field descriptions
The AMCNTENCLR1 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| P<n>, bit [n] | |||||||||||||||||||||||||||||||
P<n>, bit [n], for n = 0 to 31
Activity monitor event counter disable bit for AMEVCNTR1<n>.
Bits [31:N] are RAZ/WI. N is the value in AMCGCR.CG1NC.
Possible values of each bit are:
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMEVCNTR1<n> is disabled. When written, has no effect. |
| 0b1 |
When read, means that AMEVCNTR1<n> is enabled. When written, disables AMEVCNTR1<n>. |
On a Cold reset, this field resets to 0.
Accessing the AMCNTENCLR1
If the number of auxiliary activity monitor event counters implemented is zero, reads of AMCNTENCLR1 are RAZ/WI. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
The number of auxiliary activity monitor event counters implemented is zero exactly when AMCFGR.NCG == 0b0000.
AMCNTENCLR1 can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| AMU | 0xC24 | AMCNTENCLR1 |
Accesses on this interface are RO.