AMCR, Activity Monitors Control Register
The AMCR characteristics are:
Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups.
External register AMCR bits [31:0] are architecturally mapped to AArch64 System register AMCR_EL0[31:0] .
External register AMCR bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0] .
The power domain of AMCR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCR are RES0.
AMCR is a 32-bit register.
The AMCR bit assignments are:
HDBG, bit 
This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.
Activity monitors do not halt counting when the PE is halted in Debug state.
Activity monitors halt counting when the PE is halted in Debug state.
Accessing the AMCR
AMCR can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.