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AMPIDR0, Activity Monitors Peripheral Identification Register 0
The AMPIDR0 characteristics are:
Purpose
Provides information to identify an activity monitors component.
For more information, see 'About the Peripheral identification scheme'.
Configuration
The power domain of AMPIDR0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
Attributes
AMPIDR0 is a 32-bit register.
Field descriptions
The AMPIDR0 bit assignments are:
Bits [31:8]
Reserved, RES0.
PART_0, bits [7:0]
Part number, least significant byte.
The value of this field is IMPLEMENTATION DEFINED.
Accessing the AMPIDR0
AMPIDR0 can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
AMU | 0xFE0 | AMPIDR0 |
Accesses on this interface are RO.