CNTTIDR, Counter-timer Timer ID Register
The CNTTIDR characteristics are:
Purpose
Indicates the implemented timers in the memory map, and their features. For each value of N from 0 to 7 it indicates whether:
- Frame CNTBaseN is a view of an implemented timer.
- Frame CNTBaseN has a second view, CNTEL0BaseN.
- Frame CNTBaseN has a virtual timer capability.
Configuration
The power domain of CNTTIDR is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
Attributes
CNTTIDR is a 32-bit register.
Field descriptions
The CNTTIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Frame7 | Frame6 | Frame5 | Frame4 | Frame3 | Frame2 | Frame1 | Frame0 |
Frame<n>, bits [4n+3:4n], for n = 0 to 7
A 4-bit field indicating the features of frame CNTBase<n>.
Bit[3] of the field is RES0.
Bit[2], the FEL0 subfield, indicates whether frame CNTBase<n> has a second view, CNTEL0Base<n>. The possible values of this bit are:
Bit[2] | Meaning |
---|---|
0b0 | Frame<n> does not have a second view. The CNTEL0ACR register in the first view of the frame isRES0 |
0b1 | Frame<n> has a second view, CNTEL0Base<n>. |
If bit[0] is 0, bit[2] is RES0.
Bit[1], the FVI subfield, indicates whether both:
- Frame CNTBase<n> implements the virtual timer registers CNTV_CVAL, CNTV_TVAL, and CNTV_CTL.
- This CNTCTLBase frame implements the virtual timer offset register CNTVOFF<n>.
The possible values of bit[1] are:
Bit[1] | Meaning |
---|---|
0b0 | Frame<n> does not have virtual capability. The virtual time and offset registers areRES0. |
0b1 | Frame<n> has virtual capability. The virtual time and offset registers are implemented |
If bit[0] is 0, bit[1] is RES0.
Bit[0], the FI subfield, indicates whether frame CNTBase<n> is implemented. The possible values of this bit are:
Bit[0] | Meaning |
---|---|
0b0 | Frame<n> is not implemented. All registers associated with the frame areRES0. |
0b1 | Frame<n> is implemented |
Accessing the CNTTIDR
In a system that recognizes two Security states this register is accessible by both Secure and Non-secure accesses.
CNTTIDR can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTCTLBase | 0x008 | CNTTIDR |
Accesses on this interface are RO.