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EDAA32PFR, External Debug Auxiliary Processor Feature Register

The EDAA32PFR characteristics are:

Purpose

Provides information about implemented PE features.

Note

The register mnemonic, EDAA32PFR, is derived from previous definitions of this register that defined this register only when AArch64 was not supported at any Exception level.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

It is IMPLEMENTATION DEFINED whether EDAA32PFR is implemented in the Core power domain or in the Debug power domain.

Attributes

EDAA32PFR is a 64-bit register.

Field descriptions

The EDAA32PFR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0MSA_fracEL3EL2PMSAVMSA
313029282726252423222120191817161514131211109876543210

Bits [63:20]

Reserved, RES0.

MSA_frac, bits [19:16]

When EDAA32PFR.PMSA == 0b0000 and EDAA32PFR.VMSA == 0b1111:

Memory System Architecture fractional field. This holds the information on additional Memory System Architectures supported. Defined values are:

MSA_fracMeaning
0b0001

PMSAv8-64 supported in all translation regimes. VMSAv8-64 not supported.

0b0010

PMSAv8-64 supported in all translation regimes. In addition to PMSAv8-64, stage 1 EL1&0 translation regime also supports VMSAv8-64.

All other values are reserved.


Otherwise:

Reserved, RES0.

EL3, bits [15:12]

When EDPFR.EL3 == 0b0000:

AArch32 EL3 Exception level handling. Defined values are:

EL3Meaning
0b0000

EL3 is not implemented or can be executed in AArch64 state.

0b0001

EL3 can be executed in AArch32 state only.

All other values are reserved.

Note

EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.


Otherwise:

Reserved, RAZ.

EL2, bits [11:8]

When EDPFR.EL2 == 0b0000:

AArch32 EL2 Exception level handling. Defined values are:

EL2Meaning
0b0000

EL2 is not implemented or can be executed in AArch64 state.

0b0001

EL2 can be executed in AArch32 state only.

All other values are reserved.

Note

EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.


Otherwise:

Reserved, RAZ.

PMSA, bits [7:4]

Indicates support for a 32-bit PMSA. Defined values are:

PMSAMeaning
0b0000

PMSA-32 not supported.

0b0100

PMSAv8-32 supported.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

VMSA, bits [3:0]

When EDAA32PFR.PMSA != 0b0000:

Indicates support for a VMSA in addition to a 32-bit PMSA Defined values are:

VMSAMeaning
0b0000

VMSA not supported.

All other values are reserved.


When EDAA32PFR.PMSA == 0b0000:

Defined values are:

VMSAMeaning
0b0000

VMSAv8-64 supported.

0b1111

Memory system architecture described by EDAA32PFR.MSA_frac.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.


Otherwise:

Reserved, RAZ.

Accessing the EDAA32PFR

EDAA32PFR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0xD60EDAA32PFR

This interface is accessible as follows:

  • When IsCorePowered() and !DoubleLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register are IMPDEF.