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EDCIDSR, External Debug Context ID Sample Register

The EDCIDSR characteristics are:


Contains the sampled value of the Context ID, captured on reading EDPCSR[31:0].


EDCIDSR is in the Core power domain.

This register is present only when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented. Otherwise, direct accesses to EDCIDSR are RES0.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.


FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.


EDCIDSR is a 32-bit register.

Field descriptions

The EDCIDSR bit assignments are:


CONTEXTIDR, bits [31:0]

Context ID. The value of CONTEXTIDR that is associated with the most recent EDPCSR sample. When the most recent EDPCSR sample was generated:

  • If EL1 is using AArch64, then the Context ID is sampled from CONTEXTIDR_EL1.
  • If EL1 is using AArch32, then the Context ID is sampled from CONTEXTIDR.
  • If EL3 is implemented and is using AArch32, then CONTEXTIDR is a banked register, and EDCIDSR samples the current banked copy of CONTEXTIDR for the Security state that is associated with the most recent EDPCSR sample.

Because the value written to EDCIDSR is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether EDCIDSR is set to the original or new value if EDPCSR samples:

  • An instruction that writes to CONTEXTIDR.
  • The next Context synchronization event.
  • Any instruction executed between these two instructions.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Accessing the EDCIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.

EDCIDSR can be accessed through the external debug interface:


This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.