EDESR, External Debug Event Status Register

The EDESR characteristics are:

Purpose

Indicates the status of internally pending Halting debug events.

Configuration

EDESR is in the Core power domain.

Attributes

EDESR is a 32-bit register.

Field descriptions

The EDESR bit assignments are:

Bits [31:3]

Reserved, RES0.

SS, bit [2]

When FEAT_DoPD is implemented:

Halting step debug event pending. Possible values of this field are:

On a Cold reset, this field resets to 0.

Otherwise:

Halting step debug event pending. Possible values of this field are:

On a Warm reset, this field resets to the value in EDECR.SS.

RC, bit [1]

Reset Catch debug event pending. Possible values of this field are:

On a Warm reset, when FEAT_DoPD is implemented, this field resets to the value in CTIDEVCTL.RCE.

On a Warm reset, when FEAT_DoPD is not implemented, this field resets to the value in EDECR.RCE.

OSUC, bit [0]

OS Unlock Catch debug event pending. Possible values of this field are:

On a Warm reset, this field resets to 0.

Accessing the EDESR

If a request to clear a pending Halting debug event is received at or about the time when halting becomes allowed, it is CONSTRAINED UNPREDICTABLE whether the event is taken.

If Core power is removed while a Halting debug event is pending, it is lost. However, it might become pending again when the Core is powered back on and Cold reset.

EDESR can be accessed through the external debug interface:

This interface is accessible as follows:

• When IsCorePowered(), !DoubleLockStatus() and SoftwareLockStatus() accesses to this register are RO.
• When IsCorePowered(), !DoubleLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
• Otherwise accesses to this register generate an error response.