EDSCR, External Debug Status and Control Register
The EDSCR characteristics are:
Purpose
Main control register for the debug implementation.
Configuration
External register EDSCR bits [30:29] are architecturally mapped to AArch64 System register MDCCSR_EL0[30:29] .
EDSCR is in the Core power domain.
Attributes
EDSCR is a 32-bit register.
Field descriptions
The EDSCR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TFO | RXfull | TXfull | ITO | RXO | TXU | PipeAdv | ITE | INTdis | TDA | MA | SC2 | NS | RES0 | SDD | RES0 | HDE | RW | EL | A | ERR | STATUS | ||||||||||
TFO, bit [31]
When FEAT_TRF is implemented:
When FEAT_TRF is implemented:
Trace Filter Override. Overrides the Trace Filter controls allowing the external debugger to trace any visible Exception level.
| TFO | Meaning |
|---|---|
| 0b0 |
Trace Filter controls are not affected. |
| 0b1 |
When OSLSR_EL1.OSLK == 1, this bit can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
This bit is ignored by the PE when ExternalSecureNoninvasiveDebugEnabled() == FALSE and the Effective value of MDCR_EL3.STE == 1.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Otherwise:
Reserved, RES0.
RXfull, bit [30]
DTRRX full.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Access to this field is RO.
TXfull, bit [29]
DTRTX full.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Access to this field is RO.
ITO, bit [28]
ITR overrun.
If the PE is in Non-debug state, this bit is UNKNOWN. ITO is set to 0 on entry to Debug state.
Access to this field is RO.
RXO, bit [27]
DTRRX overrun.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Access to this field is RO.
TXU, bit [26]
DTRTX underrun.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Access to this field is RO.
PipeAdv, bit [25]
Pipeline advance. Set to 1 every time the PE pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
Access to this field is RO.
ITE, bit [24]
ITR empty.
If the PE is in Non-debug state, this bit is UNKNOWN. It is always valid in Debug state.
Access to this field is RO.
INTdis, bits [23:22]
When FEAT_Debugv8p4 is implemented:
When FEAT_Debugv8p4 is implemented:
Interrupt disable. Disables taking interrupts in Non-Debug state.
| INTdis | Meaning |
|---|---|
| 0b0 |
Masking of interrupts is controlled by PSTATE and interrupt routing controls. |
| 0b1 |
If ExternalSecureDebugEnabled() == TRUE, then all interrupts, including virtual and SError interrupts, are masked. If ExternalSecureDebugEnabled() == FALSE, then all interrupts targetting Non-secure state are masked. |
When OSLSR_EL1.OSLK == 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
This field is ignored by the PE and treated as zero when ExternalDebugEnabled() == FALSE.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Otherwise:
Interrupt disable.
When OSLSR_EL1.OSLK == 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
| INTdis | Meaning |
|---|---|
| 0b00 |
Do not disable interrupts. |
| 0b01 |
Disable interrupts taken to Non-secure EL1. |
| 0b10 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If ExternalSecureInvasiveDebugEnabled() == TRUE, also disable interrupts taken to Secure EL1. |
| 0b11 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If ExternalSecureInvasiveDebugEnabled() == TRUE, also disable all other interrupts. |
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
TDA, bit [21]
Traps accesses to the following debug System registers:
- AArch64: DBGBCR<n>_EL1, DBGBVR<n>_EL1, DBGWCR<n>_EL1, DBGWVR<n>_EL1.
- AArch32: DBGBCR<n>, DBGBVR<n>, DBGBXVR<n>, DBGWCR<n>, DBGWVR<n>.
The possible values of this field are:
| TDA | Meaning |
|---|---|
| 0b0 |
Accesses to debug System registers do not generate a Software Access Debug event. |
| 0b1 |
Accesses to debug System registers generate a Software Access Debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed. |
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
MA, bit [20]
Memory access mode. Controls the use of memory-access mode for accessing ITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.
Possible values of this field are:
| MA | Meaning |
|---|---|
| 0b0 |
Normal access mode. |
| 0b1 |
Memory access mode. |
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
SC2, bit [19]
When FEAT_PCSRv8 is implemented, (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented) and FEAT_PCSRv8p2 is not implemented:
When FEAT_PCSRv8 is implemented, (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented) and FEAT_PCSRv8p2 is not implemented:
Sample CONTEXTIDR_EL2. Controls whether the PC Sample-based Profiling Extension samples CONTEXTIDR_EL2 or VTTBR_EL2.VMID.
| SC2 | Meaning |
|---|---|
| 0b0 |
Sample VTTBR_EL2.VMID. |
| 0b1 |
Sample CONTEXTIDR_EL2. |
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Otherwise:
Reserved, RES0.
NS, bit [18]
Non-secure status. When in Debug state, gives the current Security state:
| NS | Meaning |
|---|---|
| 0b0 |
Secure state, IsSecure() == TRUE. |
| 0b1 |
Non-secure state, IsSecure() == FALSE. |
In Non-debug state, this bit is UNKNOWN.
Access to this field is RO.
Bit [17]
Reserved, RES0.
SDD, bit [16]
Secure debug disabled.
On entry to Debug state:
- If entering in Secure state, SDD is set to 0.
- If entering in Non-secure state, SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled().
In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.
In Non-debug state:
- SDD returns the inverse of ExternalSecureInvasiveDebugEnabled(). If the authentication signals that control ExternalSecureInvasiveDebugEnabled() change, a context synchronization event is required to guarantee their effect.
- This bit is unaffected by the Security state of the PE.
If EL3 is not implemented and the implementation is Non-secure, this bit is RES1.
Access to this field is RO.
Bit [15]
Reserved, RES0.
HDE, bit [14]
Halting debug enable. The possible values of this field are:
| HDE | Meaning |
|---|---|
| 0b0 |
Halting disabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
| 0b1 |
Halting enabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
RW, bits [13:10]
Exception level Execution state status. In Debug state, each bit gives the current Execution state of each Exception level.
| RW | Meaning | Applies when |
|---|---|---|
| 0b1111 |
All Exception levels are using AArch64 or the PE is in Non-debug state. | |
| 0b1110 |
The PE is in Debug state. EL0 is using AArch32. All other Exception levels are using AArch64. Only permitted if the PE is executing at EL0. | When AArch32 is supported at any Exception level |
| 0b110x |
The PE is in Debug state. EL0 and EL1 are using AArch32. EL2 and EL3 are using AArch64. Only permitted if EL2 is implemented and enabled in the current Security state. | When AArch32 is supported at any Exception level |
| 0b10xx |
The PE is in Debug state. EL0, EL1, and, if implemented in the current Security state, EL2 are using AArch32. EL3 is using AArch64. | When AArch32 is supported at any Exception level, EL3 is implemented, EL3 is using AArch64 and EL2 is implemented |
| 0b0xxx |
The PE is in Debug state. All Exception levels are using AArch32. | When AArch32 is supported at any Exception level |
In Non-debug state, this field is RAO.
Access to this field is RO.
EL, bits [9:8]
Exception level. In Debug state, this gives the current Exception level of the PE.
In Non-debug state, this field is RAZ.
Access to this field is RO.
A, bit [7]
SError interrupt pending. In Debug state, indicates whether an SError interrupt is pending:
- If HCR_EL2.{AMO, TGE} = {1, 0}, EL2 is enabled in the current Security state, and the PE is executing at EL0 or EL1, a virtual SError interrupt.
- Otherwise, a physical SError interrupt.
| A | Meaning |
|---|---|
| 0b0 |
No SError interrupt pending. |
| 0b1 |
SError interrupt pending. |
A debugger can read EDSCR to check whether an SError interrupt is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.
UNKNOWN in Non-debug state.
Access to this field is RO.
ERR, bit [6]
Cumulative error flag. This bit is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Access to this field is RO.
STATUS, bits [5:0]
Debug status flags.
| STATUS | Meaning |
|---|---|
| 0b000001 |
PE is restarting, exiting Debug state. |
| 0b000010 |
PE is in Non-debug state. |
| 0b000111 |
Breakpoint. |
| 0b010011 |
External debug request. |
| 0b011011 |
Halting step, normal. |
| 0b011111 |
Halting step, exclusive. |
| 0b100011 |
OS Unlock Catch. |
| 0b100111 |
Reset Catch. |
| 0b101011 |
Watchpoint. |
| 0b101111 |
HLT instruction. |
| 0b110011 |
Software access to debug register. |
| 0b110111 |
Exception Catch. |
| 0b111011 |
Halting step, no syndrome. |
All other values of STATUS are reserved.
Access to this field is RO.
Accessing the EDSCR
EDSCR can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| Debug | 0x088 | EDSCR |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.