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EDVIDSR, External Debug Virtual Context Sample Register

The EDVIDSR characteristics are:

Purpose

Contains sampled values captured on reading EDPCSR[31:0].

Configuration

EDVIDSR is in the Core power domain.

This register is present only when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented. Otherwise, direct accesses to EDVIDSR are RES0.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.

When the PC Sample-based Profiling Extension is implemented in the external debug registers space, if EL2 is not implemented and EL3 is not implemented, it is IMPLEMENTATION DEFINED whether EDVIDSR is implemented.

Note

FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.

Attributes

If FEAT_VHE is implemented, the format of this register differs depending on the value of EDSCR.SC2.

Field descriptions

The EDVIDSR bit assignments are:

When FEAT_VHE is not implemented or EDSCR.SC2 == 0:
313029282726252423222120191817161514131211109876543210
NSE2E3HVRES0VMID[15:8]VMID

This format applies in all Armv8.0 implementations.

NS, bit [31]

Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.

If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.

NSMeaning
0b0

Sample is from Secure state.

0b1

Sample is from Non-secure state.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

E2, bit [30]

When EL2 is implemented:

Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.

E2Meaning
0b0

Sample is not from EL2.

0b1

Sample is from EL2.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

E3, bit [29]

When EL3 is implemented and the highest implemented Exception level is using AArch64 state:

Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.

E3Meaning
0b0

Sample is not from EL3 using AArch64.

0b1

Sample is from EL3 using AArch64.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

HV, bit [28]

EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:

HVMeaning
0b0

Bits[63:32] of the most recent EDPCSR sample are zero.

0b1

Bits[63:32] of the most recent EDPCSR sample might be nonzero.

An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero. An EDVIDSR.HV value of 0 is a hint that EDPCSRhi (EDPCSR[63:32]) does not need to be read.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Bits [27:16]

Reserved, RES0.

VMID[15:8], bits [15:8]

When FEAT_VMID16 is implemented and EL2 is implemented:

Extension to VMID[7:0]. See VMID[7:0] for more details.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

VMID, bits [7:0]

When EL2 is implemented:

VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample. When the most recent EDPCSR sample was generated:

  • This field is RES0 if any of the following apply:
    • The PE is executing in Secure state.
    • The PE is executing at EL2.
  • Otherwise:
    • If EL2 is using AArch64 and either FEAT_VMID16 is not implemented or VTCR_EL2.VS is 1, this field is set to VTTBR_EL2.VMID.
    • If EL2 is using AArch64, FEAT_VMID16 is implemented, and VTCR_EL2.VS is 0, PMVIDSR.VMID[7:0] is set to VTTBR_EL2.VMID[7:0] and PMVIDSR.VMID[15:8] is RES0.
    • If EL2 is using AArch32, this field is set to VTTBR.VMID.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

When (FEAT_VHE is implemented or FEAT_Debugv8p2 is implemented) and EDSCR.SC2 == 1:
313029282726252423222120191817161514131211109876543210
CONTEXTIDR_EL2

CONTEXTIDR_EL2, bits [31:0]

Context ID. The value of CONTEXTIDR_EL2 that is associated with the most recent EDPCSR sample. When the most recent EDPCSR sample was generated:

  • If EL2 was using AArch64 and the PE was executing in Non-secure state, then this field is set to the Context ID sampled from CONTEXTIDR_EL2.
  • If EL2 was using AArch32 or the PE was executing in Secure state, then this field is set to an UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Accessing the EDVIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.

EDVIDSR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x0A8EDVIDSR

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.