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ERRGSR, Error Group Status Register
The ERRGSR characteristics are:
Purpose
Shows the status for the records in the group.
Configuration
ERRGSR is implemented only as part of a memory-mapped group of error records.
This manual describes a group of error records accessed via a standard 4KB memory-mapped peripheral. For a 4KB peripheral, up to 24 error records can be accessed if the Common Fault Injection Model is implemented, and up to 56 otherwise.
Attributes
ERRGSR is a 64-bit register.
Field descriptions
The ERRGSR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | S<m>, bit [m] | ||||||||||||||||||||||||||||||
S<m>, bit [m] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:56]
Reserved, RES0.
S<m>, bit [m], for m = 0 to 55
When error record <m> is implemented and error record <m> supports this type of reporting:
When error record <m> is implemented and error record <m> supports this type of reporting:
The status for error record <m>. A read-only copy of ERR<m>STATUS.V.
S<m> | Meaning |
---|---|
0b0 |
No error. |
0b1 |
One or more errors. |
If the Common Fault Injection Model is implemented, up-to 24 records can be implemented meaning bits [55:24] are RES0.
Otherwise:
Otherwise:
Reserved, RES0.
Accessing the ERRGSR
ERRGSR can be accessed through the memory-mapped interfaces:
Component | Offset |
---|---|
RAS | 0xE00 |
Accesses on this interface are RO.