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ERRIRQSR, Error Interrupt Status Register

The ERRIRQSR characteristics are:

Purpose

Interrupt status register.

Configuration

This register is present only when interrupt configuration registers are implemented. Otherwise, direct accesses to ERRIRQSR are RES0.

ERRIRQSR is implemented only as part of a memory-mapped group of error records.

Attributes

ERRIRQSR is a 64-bit register.

Field descriptions

The ERRIRQSR bit assignments are:

When the implementation uses the recommended layout for the ERRIRQCR<n> registers:
6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0CRIERRCRIERIERRERIFHIERRFHI

Bits [63:6]

Reserved, RES0.

CRIERR, bit [5]

When the Critical Error Interrupt is implemented:

Critical Error Interrupt error.

CRIERRMeaning
0b0

Critical Error Interrupt write has not returned an error since this bit was last cleared to zero.

0b1

Critical Error Interrupt write has returned an error since this bit was last cleared to zero.

This bit is read/write-one-to-clear.

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

CRI, bit [4]

When the Critical Error Interrupt is implemented:

Critical Error Interrupt write in progress.

CRIMeaning
0b0

Critical Error Interrupt write not in progress.

0b1

Critical Error Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.


Otherwise:

Reserved, RES0.

ERIERR, bit [3]

When the Error Recovery Interrupt is implemented:

Error Recovery Interrupt error.

ERIERRMeaning
0b0

Error Recovery Interrupt write has not returned an error since this bit was last cleared to zero.

0b1

Error Recovery Interrupt write has returned an error since this bit was last cleared to zero.

This bit is read/write-one-to-clear.

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

ERI, bit [2]

When the Error Recovery Interrupt is implemented:

Error Recovery Interrupt write in progress.

ERIMeaning
0b0

Error Recovery Interrupt write not in progress.

0b1

Error Recovery Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.


Otherwise:

Reserved, RES0.

FHIERR, bit [1]

When the Fault Handling Interrupt is implemented:

Fault Handling Interrupt error.

FHIERRMeaning
0b0

Fault Handling Interrupt write has not returned an error since this bit was last cleared to zero.

0b1

Fault Handling Interrupt write has returned an error since this bit was last cleared to zero.

This bit is read/write-one-to-clear.

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

FHI, bit [0]

When the Fault Handling Interrupt is implemented:

Fault Handling Interrupt write in progress.

FHIMeaning
0b0

Fault Handling Interrupt write not in progress.

0b1

Fault Handling Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.


Otherwise:

Reserved, RES0.

When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:
6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing the ERRIRQSR

ERRIRQSR can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xEF8

Accesses on this interface are RW.