ERR<n>MISC1, Error Record Miscellaneous Register 1, n = 0 - 65534
The ERR<n>MISC1 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:
- Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.
- A Corrected error counter or counters.
- Other state information not present in the corresponding status and address registers.
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>MISC1 are RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>MISC1, writing zero returns the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
Arm recommends that any IMPLEMENTATION DEFINED syndrome field that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request is disabled at Cold reset and is enabled by software writing an IMPLEMENTATION DEFINED nonzero value to an IMPLEMENTATION DEFINED field in ERR<q>CTLR.
ERR<n>MISC1 is a 64-bit register.
The ERR<n>MISC1 bit assignments are:
IMPLEMENTATION DEFINED, bits [63:0]
IMPLEMENTATION DEFINED syndrome.
Accessing the ERR<n>MISC1
Reads from ERR<n>MISC1 return an IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.
If the Common Fault Injection Mechanism is implemented by the node that owns this error record, and ERR<q>PFGF.MV is 0b1, then some parts of this register are read/write when ERR<n>STATUS.MV == 0b1. See ERR<n>PFGF.MV for more information.
For other parts of this register, or if the Common Fault Injection Mechanism is not implemented, then Arm recommends that:
- Miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.
- When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error ignores writes.
These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.
ERR<n>MISC1 can be accessed through the memory-mapped interfaces:
|RAS||0x028 + (64 * n)||ERR<n>MISC1|
Accesses on this interface are RW.