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GICC_NSAPR<n>, CPU Interface Non-secure Active Priorities Registers, n = 0 - 3
The GICC_NSAPR<n> characteristics are:
Purpose
Provides information about Group 1 interrupt active priorities.
Configuration
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses.
GICC_NSAPR1 is only implemented in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are only implemented in implementations that support 7 bits of priority.
Attributes
GICC_NSAPR<n> is a 32-bit register.
Field descriptions
The GICC_NSAPR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED, bits [31:0]
IMPLEMENTATION DEFINED.
This field resets to 0.
Accessing the GICC_NSAPR<n>
GICC_NSAPR<n> can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x00E0 + (4 * n) | GICC_NSAPR<n> |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.