GICD_ICACTIVER<n>, Interrupt Clear-Active Registers, n = 0 - 31
The GICD_ICACTIVER<n> characteristics are:
Purpose
Deactivates the corresponding interrupt. These registers are used when saving and restoring GIC state.
Configuration
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
The number of implemented GICD_ICACTIVER<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_ICACTIVER0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICACTIVER0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
Attributes
GICD_ICACTIVER<n> is a 32-bit register.
Field descriptions
The GICD_ICACTIVER<n> bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Clear_active_bit<x>, bit [x], for x = 0 to 31 | |||||||||||||||||||||||||||||||
Clear_active_bit<x>, bit [x], for x = 0 to 31
Removes the active state from interrupt number 32n + x. Reads and writes have the following behavior:
| Clear_active_bit<x> | Meaning |
|---|---|
| 0b0 |
If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect. |
| 0b1 |
If read, indicates that the corresponding interrupt is active, or is active and pending. If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect. |
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_ICACTIVER<n> number, n, is given by n = m DIV 32.
- The offset of the required GICD_ICACTIVER is (0x380 + (4*n)).
- The bit number of the required group modifier bit in this register is m MOD 32.
Accessing the GICD_ICACTIVER<n>
When affinity routing is enabled for the Security state of an interrupt, the bits corresponding to SGIs and PPIs in that Security state are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ICACTIVER0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.
GICD_ICACTIVER<n> can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Distributor | 0x0380 + (4 * n) | GICD_ICACTIVER<n> |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.