GICD_IGROUPR<n>, Interrupt Group Registers, n = 0 - 31
The GICD_IGROUPR<n> characteristics are:
Controls whether the corresponding interrupt is in Group 0 or Group 1.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Secure.
The number of implemented GICD_IGROUPR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_IGROUPR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_IGROUPR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
GICD_IGROUPR<n> is a 32-bit register.
The GICD_IGROUPR<n> bit assignments are:
|Group_status_bit<x>, bit [x], for x = 0 to 31|
Group_status_bit<x>, bit [x], for x = 0 to 31
Group status bit.
When GICD_CTLR.DS==1, the corresponding interrupt is Group 0.
When GICD_CTLR.DS==0, the corresponding interrupt is Secure.
When GICD_CTLR.DS==1, the corresponding interrupt is Group 1.
When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.
If affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGRPMODR<n> to form a 2-bit field that defines an interrupt group. The encoding of this field is described in GICD_IGRPMODR<n>.
If affinity routing is disabled for the Security state of an interrupt, then:
- The corresponding GICD_IGRPMODR<n> bit is RES0.
- For Secure interrupts, the interrupt is Secure Group 0.
- For Non-secure interrupts, the interrupt is Non-secure Group 1.
When n == 0, this field resets to an UNKNOWN value.
When n > 0, this field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_IGROUP<n> number, n, is given by n = m DIV 32.
- The offset of the required GICD_IGROUP is (0x080 + (4*n)).
- The bit number of the required group modifier bit in this register is m MOD 32.
Accessing the GICD_IGROUPR<n>
For SGIs and PPIs:
- When ARE is 1 for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case.
- Equivalent functionality is provided by GICR_IGROUPR0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Accesses to GICD_IGROUPR0 when affinity routing is not enabled for a Security state access the same state as GICR_IGROUPR0, and must update Redistributor state associated with the PE performing the accesses. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
GICD_IGROUPR<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0080 + (4 * n)||GICD_IGROUPR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.