GICD_ISACTIVER<n>E, Interrupt Set-Active Registers (extended SPI range), n = 0 - 31
The GICD_ISACTIVER<n>E characteristics are:
Adds the active state to the corresponding SPI in the extended SPI range.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ISACTIVER<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ISACTIVER<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
GICD_ISACTIVER<n>E is a 32-bit register.
The GICD_ISACTIVER<n>E bit assignments are:
|Set_active_bit<x>, bit [x], for x = 0 to 31|
Set_active_bit<x>, bit [x], for x = 0 to 31
For the extended SPIs, adds the active state to interrupt number x. Reads and writes have the following behavior:
If read, indicates that the corresponding interrupt is not active, and is not active and pending.
If written, has no effect.
If read, indicates that the corresponding interrupt is active, or active and pending on this PE.
If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect.
After a write of 1 to this bit, a subsequent read of this bit returns 1.
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_ISACTIVER<n>E number, n, is given by n = (m-4096) DIV 32.
- The offset of the required GICD_ISACTIVER<n>E is (0x1A00 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
Accessing the GICD_ISACTIVER<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICD_ISACTIVER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICD_ISACTIVER<n>E can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x1A00 + (4 * n)||GICD_ISACTIVER<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.