GICD_SGIR, Software Generated Interrupt Register
The GICD_SGIR characteristics are:
Controls the generation of SGIs.
This register is available in all configurations of the GIC. If the GIC supports two Security states this register is Common.
GICD_SGIR is a 32-bit register.
The GICD_SGIR bit assignments are:
TargetListFilter, bits [25:24]
Determines how the Distributor processes the requested SGI.
Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList.
Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt.
Forward the interrupt only to the CPU interface of the PE that requested the interrupt.
CPUTargetList, bits [23:16]
When GICD_SGIR.TargetListFilter is 0b00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.
Each bit of the field refers to the corresponding CPU interface. For example, CPUTargetList corresponds to interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface.
If this field is 0b00000000 when GICD_SGIR.TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface.
NSATT, bit 
Specifies the required group of the SGI.
Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface.
Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 1 on that interface.
This field is writable only by a Secure access. Non-secure accesses can also generate Group 0 interrupts, if allowed to do so by GICD_NSACR0. Otherwise, Non-secure writes to GICD_SGIR generate an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit  of the write.
INTID, bits [3:0]
The INTID of the SGI to forward to the specified CPU interfaces.
Accessing the GICD_SGIR
This register is used only when affinity routing is not enabled. When affinity routing is enabled, this register is RES0.
It is IMPLEMENTATION DEFINED whether this register has any effect when the forwarding of interrupts by the Distributor is disabled by GICD_CTLR.
GICD_SGIR can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.