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GICH_EISR, End Interrupt Status Register

The GICH_EISR characteristics are:

Purpose

Indicates which List registers have outstanding EOI maintenance interrupts.

Configuration

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_EISR is a 32-bit register.

Field descriptions

The GICH_EISR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0Status<n>, bit [n], for n = 0 to 15

Bits [31:16]

Reserved, RES0.

Status<n>, bit [n], for n = 0 to 15

EOI maintenance interrupt status for List register <n>:

Status<n>Meaning
0b0

GICH_LR<n> does not have an EOI maintenance interrupt.

0b1

GICH_LR<n> has an EOI maintenance interrupt that has not been handled.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:

This field resets to an architecturally UNKNOWN value.

Accessing the GICH_EISR

This register is used only when System register access is not enabled. When System register access is enabled:

  • For AArch32 implementations, ICH_EISR provides equivalent functionality.
  • For AArch64 implementations, ICH_EISR_EL2 provides equivalent functionality.

Bits corresponding to unimplemented List registers are RAZ.

GICH_EISR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Virtual interface control0x0020GICH_EISR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RO.
  • When an access is Secure accesses to this register are RO.
  • When an access is Non-secure accesses to this register are RO.