GICH_ELRSR, Empty List Register Status Register
The GICH_ELRSR characteristics are:
Indicates which List registers contain valid interrupts.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_ELRSR is a 32-bit register.
The GICH_ELRSR bit assignments are:
Status<n>, bit [n], for n = 0 to 15
Status bit for List register <n>:
GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt.
GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt.
This field resets to 1.
Accessing the GICH_ELRSR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICH_ELRSR provides equivalent functionality.
- For AArch64 implementations, ICH_ELRSR_EL2 provides equivalent functionality.
Bits corresponding to unimplemented List registers are RES0.
GICH_ELRSR can be accessed through the memory-mapped interfaces:
|GIC Virtual interface control||0x0030||GICH_ELRSR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.