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GICH_ELRSR, Empty List Register Status Register

The GICH_ELRSR characteristics are:

Purpose

Indicates which List registers contain valid interrupts.

Configuration

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_ELRSR is a 32-bit register.

Field descriptions

The GICH_ELRSR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0Status<n>, bit [n], for n = 0 to 15

Bits [31:16]

Reserved, RES0.

Status<n>, bit [n], for n = 0 to 15

Status bit for List register <n>:

Status<n>Meaning
0b0

GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt.

0b1

GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if GICH_LR<n>.State is 0b00 and either:

This field resets to 1.

Accessing the GICH_ELRSR

This register is used only when System register access is not enabled. When System register access is enabled:

  • For AArch32 implementations, ICH_ELRSR provides equivalent functionality.
  • For AArch64 implementations, ICH_ELRSR_EL2 provides equivalent functionality.

Bits corresponding to unimplemented List registers are RES0.

GICH_ELRSR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Virtual interface control0x0030GICH_ELRSR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RO.
  • When an access is Secure accesses to this register are RO.
  • When an access is Non-secure accesses to this register are RO.


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