GICR_ICENABLER<n>E, Interrupt Clear-Enable Registers, n = 1 - 2
The GICR_ICENABLER<n>E characteristics are:
Disables forwarding of the corresponding PPI to the CPU interfaces.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ICENABLER<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ICENABLER<n>E is a 32-bit register.
The GICR_ICENABLER<n>E bit assignments are:
|Clear_enable_bit<x>, bit [x], for x = 0 to 31|
Clear_enable_bit<x>, bit [x], for x = 0 to 31
For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
If read, indicates that forwarding of the corresponding interrupt is disabled.
If written, has no effect.
If read, indicates that forwarding of the corresponding interrupt is enabled.
If written, disables forwarding of the corresponding interrupt.
After a write of 1 to this bit, a subsequent read of this bit returns 0.
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICR_ICENABLER<n>E number, n, is given by n = (m-1024) DIV 32.
- The offset of the required GICR_ICENABLER<n>E is (0x180 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-1024) MOD 32.
Accessing the GICR_ICENABLER<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICR_ICENABLER<n>E can be accessed through the memory-mapped interfaces:
|GIC Redistributor||SGI_base||0x0180 + (4 * n)||GICR_ICENABLER<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.