GICV_AIAR, Virtual Machine Aliased Interrupt Acknowledge Register
The GICV_AIAR characteristics are:
Provides the INTID of the signaled Group 1 virtual interrupt. A read of this register by the PE acts as an acknowledge for the interrupt.
This register corresponds to the physical CPU interface register GICC_AIAR.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_AIAR is a 32-bit register.
The GICV_AIAR bit assignments are:
INTID, bits [24:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
The operation of this register is similar to the operation of GICV_IAR. When a vPE reads this register, the corresponding GICH_LR<n>.Group field is checked to determine whether the interrupt is in Group 0 or Group 1:
- If the interrupt is Group 0, the spurious INTID 1023 is returned and the interrupt is not acknowledged.
- If the interrupt is Group 1, the INTID is returned. The List register entry is updated to active state, and the appropriate bit in GICH_APR<n> is set to 1.
A read of this register returns the spurious INTID 1023 if any of the following are true:
- When the virtual CPU interface is enabled and GICH_HCR.En == 1:
- There are no pending interrupts of sufficiently high priority value to be signaled to the PE.
- The highest priority pending interrupt is in Group 0.
- Interrupt signaling by the virtual CPU interface is disabled.
Accessing the GICV_AIAR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_IAR1 provides equivalent functionality.
- For AArch64 implementations, ICC_IAR1_EL1 provides equivalent functionality.
This register is used for Group 1 interrupts only. GICV_IAR provides equivalent functionality for Group 0 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
GICV_AIAR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x0020||GICV_AIAR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.