GITS_CTLR, ITS Control Register
The GITS_CTLR characteristics are:
Controls the operation of an ITS.
The ITS_Number (bits [7:4]) and bit  fields apply only in FEAT_GICv4 implementations, and are RES0 in FEAT_GICv3 implementations.
GITS_CTLR is a 32-bit register.
The GITS_CTLR bit assignments are:
Quiescent, bit 
Read-only. Indicates completion of all ITS operations when GITS_CTLR.Enabled == 0.
The ITS is not quiescent and cannot be powered down.
The ITS is quiescent and can be powered down.
For the ITS to be considered inactive, there must be no transactions in progress. In addition, all operations required to ensure that mapping data is consistent with external memory must be complete.
In distributed GIC implementations, this bit is set to 1 only after the ITS forwards any operations that have not yet been completed to the Redistributors and receives confirmation that all such operations have reached the appropriate Redistributor.
In FEAT_GICv3, FEAT_GICv3p1, and FEAT_GICv4, when GITS_CTLR.Enabled == 1, the value of GITS_CTLR.Quiescent is UNKNOWN.
In FEAT_GICv4p1, when GITS_CTLR.Enabled == 1, the value of GITS_CTLR.Quiescent reads as 1 until the write to Enabled has taken effect and then reads as 0.
This field resets to 1.
ITS_Number, bits [7:4]
In FEAT_GICv3 implementations this field is RES0.
In FEAT_GICv4 implementations with more than one ITS instance, this field indicates the ITS number for use with 'VMOVP GICv4.0' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
It is IMPLEMENTATION DEFINED whether this field is programmable or RO.
If this field is programmable, changing this field when GITS_CTLR.Quiescent == 0 or GITS_CTLR.Enabled == 1 is UNPREDICTABLE.
This field resets to an architecturally UNKNOWN value.
ImDe, bit 
In GICv3 implementations, this bit is RES0.
In GICv4 implementations, this bit is IMPLEMENTATION DEFINED.
This field resets to 0.
Enabled, bit 
Controls whether the ITS is enabled:
The ITS is not enabled. Writes to GITS_TRANSLATER are ignored and no further command queue entries are processed.
The ITS is enabled. Writes to GITS_TRANSLATER result in interrupt translations and the command queue is processed.
If a write to this register changes this field from 1 to 0, the ITS must ensure that both:
- Any caches containing mapping data are made consistent with external memory.
- GITS_CTLR.Quiescent == 0 until all caches are consistent with external memory.
Changing GITS_CTLR.Enabled from 0 to 1 when GITS_CTLR.Quiescent is 0 results in UNPREDICTABLE behavior.
This field resets to 0.
Accessing the GITS_CTLR
GITS_CTLR can be accessed through the memory-mapped interfaces:
|GIC ITS control||0x0000||GITS_CTLR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.