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MPAMF_ESR, MPAM Error Status Register

The MPAMF_ESR characteristics are:

Purpose

Indicates MPAM error status for this MSC. MPAMF_ESR_s reports Secure MPAM errors. MPAMF_ESR_ns reports Non-secure MPAM errors.

Software should write this register after reading the status of an error to reset ERRCODE to 0x0000 and OVRWR to 0 so that future errors are not reported with OVRWR set.

Configuration

The power domain of MPAMF_ESR is IMPLEMENTATION DEFINED.

If a MSC cannot encounter any of the error conditions listed in 'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.

Attributes

MAMPF_ESR is 64-bit register when MPAM v0.1 or v1.1 is implemented and MPAMF_IDR.HAS_EXTD_ESR == 1.

Otherwise, MAMPF_ESR is a 32-bit register.

Field descriptions

The MPAMF_ESR bit assignments are:

When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMF_IDR.HAS_EXTD_ESR == 1:
6362616059585756555453525150494847464544434241403938373635343332
RES0RIS
OVRWRRES0ERRCODEPMGPARTID_MON

Bits [63:36]

Reserved, RES0.

RIS, bits [35:32]

When MPAMF_IDR.HAS_RIS == 1:

Resource Instance Selector. Where applicable to the ERRCODE, captures the RIS value for the error.


Otherwise:

Reserved, RES0.

OVRWR, bit [31]

Overwritten.

If 0 and ERRCODE == 0b0000, no errors have occurred.

If 0 and ERRCODE is non-zero, a single error has occurred and is recorded in this register.

If 1 and ERRCODE is non-zero, multiple errors have occurred and this register records the most recent error.

The state where this bit is 1 and ERRCODE is zero must not be produced by hardware and is only reached when software writes this combination into this register.

Bits [30:28]

Reserved, RES0.

ERRCODE, bits [27:24]

Error code.

ERRCODEMeaning
0b0000

No error.

0b0001

PARTID_SEL_Range.

0b0010

Req_PARTID_Range.

0b0011

MSMONCFG_ID_RANGE.

0b0100

Req_PMG_Range.

0b0101

Monitor_Range.

0b0110

intPARTID_Range.

0b0111

Unexpected_INTERNAL.

0b1000

Undefined_RIS_PART_SEL.

0b1001

RIS_No_Control.

0b1010

Undefined_RIS_MON_SEL.

0b1011

RIS_No_Monitor.

0b1100

Reserved.

0b1101

Reserved.

0b1110

Reserved.

0b1111

Reserved.

PMG, bits [23:16]

Program monitoring group.

Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG.

PARTID_MON, bits [15:0]

PARTID or monitor.

Set to the PARTID on an error that captures PARTID.

Set to the monitor index on an error that captures MON.

On an error that captures neither PARTID nor MON, this field is set to 0.

Otherwise:
313029282726252423222120191817161514131211109876543210
OVRWRRES0ERRCODEPMGPARTID_MON
313029282726252423222120191817161514131211109876543210

OVRWR, bit [31]

Overwritten.

If 0 and ERRCODE == 0b0000, no errors have occurred.

If 0 and ERRCODE is non-zero, a single error has occurred and is recorded in this register.

If 1 and ERRCODE is non-zero, multiple errors have occurred and this register records the most recent error.

The state where this bit is 1 and ERRCODE is 0 must not be produced by hardware and is only reached when software writes this combination into this register.

Bits [30:28]

Reserved, RES0.

ERRCODE, bits [27:24]

Error code.

ERRCODEMeaning
0b0000

No error.

0b0001

PARTID_SEL_Range.

0b0010

Req_PARTID_Range.

0b0011

MSMONCFG_ID_RANGE.

0b0100

Req_PMG_Range.

0b0101

Monitor_Range.

0b0110

intPARTID_Range.

0b0111

Unexpected_INTERNAL.

0b1000

Reserved.

0b1001

Reserved.

0b1010

Reserved.

0b1011

Reserved.

0b1100

Reserved.

0b1101

Reserved.

0b1110

Reserved.

0b1111

Reserved.

PMG, bits [23:16]

Program monitoring group.

Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG.

PARTID_MON, bits [15:0]

PARTID or monitor.

Set to the PARTID on an error that captures PARTID.

Set to the monitor index on an error that captures MON.

On an error that captures neither PARTID nor MON, this field is set to 0x0000.

Accessing the MPAMF_ESR

This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.

MPAMF_ESR_s must be accessible from the Secure MPAM feature page. MPAMF_ESR_ns must be accessible from the Non-secure MPAM feature page.

MPAMF_ESR_s and MPAMF_ESR_ns must be separate registers. The Secure instance (MPAMF_ESR_s) accesses the error status used for Secure PARTIDs, and the Non-secure instance (MPAMF_ESR_ns) accesses the error status used for Non-secure PARTIDs.

MPAMF_ESR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x00F8MPAMF_ESR_s

Accesses on this interface are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x00F8MPAMF_ESR_ns

Accesses on this interface are RW.