MSMON_CFG_MBWU_CTL, MPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
The MSMON_CFG_MBWU_CTL characteristics are:
Purpose
Controls the MBWU monitor selected by MSMON_CFG_MON_SEL. MSMON_CFG_MBWU_CTL_s controls the Secure memory bandwidth usage monitor instance selected by the Secure instance of MSMON_CFG_MON_SEL. MSMON_CFG_MBWU_CTL_ns controls Non-secure memory bandwidth usage monitor instance selected by the Non-secure instance of MSMON_CFG_MON_SEL.
If MPAMF_IDR.HAS_RIS is 1, the monitor instance configuration accessed is for the resource instance currently selected by MSMON_CFG_MON_SEL.RIS and the monitor instance of that resource instance selected by MSMON_CFG_MON_SEL.MON_SEL.
Configuration
The power domain of MSMON_CFG_MBWU_CTL is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_MSMON == 1 and MPAMF_MSMON_IDR.MSMON_MBWU == 1. Otherwise, direct accesses to MSMON_CFG_MBWU_CTL are RES0.
Attributes
MSMON_CFG_MBWU_CTL is a 32-bit register.
Field descriptions
The MSMON_CFG_MBWU_CTL bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN | CAPT_EVNT | CAPT_RESET | OFLOW_STATUS | OFLOW_INTR | OFLOW_FRZ | SUBTYPE | SCLEN | RES0 | MATCH_PMG | MATCH_PARTID | OFLOW_STATUS_L | OFLOW_INTR_L | RES0 | TYPE | |||||||||||||||||
EN, bit [31]
Enabled.
| EN | Meaning |
|---|---|
| 0b0 |
The monitor instance is disabled and must not collect any information. |
| 0b1 |
The monitor instance is enabled to collect information according to the configuration of the instance. |
CAPT_EVNT, bits [30:28]
Capture event selector.
When the selected capture event occurs, MSMON_MBWU of the monitor instance is copied to MSMON_MBWU_CAPTURE of the same instance. If the long counter is also implemented, MSMON_MBWU_L is also copied to MSMON_MBWU_L_CAPTURE.
Select the event that triggers capture from the following:
| CAPT_EVNT | Meaning |
|---|---|
| 0b000 |
No capture event is triggered. |
| 0b001 |
External capture event 1 (optional but recommended) |
| 0b010 |
External capture event 2 (optional) |
| 0b011 |
External capture event 3 (optional) |
| 0b100 |
External capture event 4 (optional) |
| 0b101 |
External capture event 5 (optional) |
| 0b110 |
External capture event 6 (optional) |
| 0b111 |
Capture occurs when a MSMON_CAPT_EVNT register in this MSC is written and causes a capture event for the security state of this monitor. (optional) |
The values marked as optional indicate capture event sources that can be omitted in an implementation. Those values representing non-implemented event sources must not trigger a capture event.
If capture is not implemented for the MBWU monitor type as indicated by MPAMF_MBWUMON_IDR.HAS_CAPTURE = 0, this field is RAZ/WI.
CAPT_RESET, bit [27]
Reset MSMON_MBWU.VALUE after capture.
Controls whether the VALUE field of the monitor instance is reset to zero immediately after being copied to the corresponding capture register.
| CAPT_RESET | Meaning |
|---|---|
| 0b0 |
MSMON_MBWU.VALUE field of the monitor instance is not reset on capture. |
| 0b1 |
MSMON_MBWU.VALUE field of the monitor instance is reset on capture. |
If capture is not implemented for the MBWU monitor type as indicated by MPAMF_MBWUMON_IDR.HAS_CAPTURE = 0, this field is RAZ/WI.
This control bit affects both MSMON_MBWU and MSMON_MBWU_L in implementations that include MSMON_MBWU_L.
OFLOW_STATUS, bit [26]
Overflow status.
Indicates whether the value of MSMON_MBWU has overflowed.
| OFLOW_STATUS | Meaning |
|---|---|
| 0b0 |
MSMON_MBWU.VALUE has not overflowed. |
| 0b1 |
MSMON_MBWU.VALUE has overflowed at least once since this bit was last written to zero. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
Overflow status for MSMON_MBWU_L.VALUE is reported in MSMON_CFG_MBWU_CTL.OFLOW_STATUS_L.
OFLOW_INTR, bit [25]
Enable interrupt on overflow of MSMON_MBWU.VALUE.
| OFLOW_INTR | Meaning |
|---|---|
| 0b0 |
No interrupt is signaled on an overflow of MSMON_MBWU.VALUE. |
| 0b1 |
An implementation-specific interrupt is signaled on an overflow of MSMON_MBWU.VALUE. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
If overflow interrupt is not supported by the MSC implementation, this field is RAZ/WI.
Interrupt enable for overflow of MSMON_MBWU_L.VALUE is controlled by MSMON_CFG_MBWU_CTL.OFLOW_INTR_L.
OFLOW_FRZ, bit [24]
Freeze monitor instance on overflow.
Controls whether MSMON_MBWU.VALUE field of the monitor instance freezes on an overflow.
| OFLOW_FRZ | Meaning |
|---|---|
| 0b0 |
MSMON_MBWU.VALUE field of the monitor instance wraps on overflow. |
| 0b1 |
MSMON_MBWU.VALUE field of the monitor instance freezes on overflow. If the increment that caused the overflow was 1, the frozen value is the post-increment value of 0. If the increment that caused the overflow was larger than 1, the frozen value of the monitor might be 0 or a larger value less than the final increment. |
If overflow is not possible for the instance of the MBWU monitor in the implementation, this field is RAZ/WI.
This control bit affects both MSMON_MBWU and MSMON_MBWU_L in implementations that include MSMON_MBWU_L.
SUBTYPE, bits [23:20]
Subtype. Type of bandwidth counted by this monitor.
This field is not currently used for MBWU monitors, but reserved for future use.
This field is RAZ/WI.
SCLEN, bit [19]
MSMON_MBWU.VALUE Scaling Enable.
Enables scaling of MSMON_MBWU.VALUE by MPAMF_MBWUMON_IDR.SCALE.
| SCLEN | Meaning |
|---|---|
| 0b0 |
MSMON_MBWU.VALUE has bytes counted by the monitor instance. |
| 0b1 |
MSMON_MBWU.VALUE has bytes counted by the monitor instance, shifted right by MPAMF_MBWUMON_IDR.SCALE. |
Bit [18]
Reserved, RES0.
MATCH_PMG, bit [17]
Match PMG.
Controls whether the monitor instance only counts data transferred with PMG matching MSMON_CFG_MBWU_FLT.PMG.
| MATCH_PMG | Meaning |
|---|---|
| 0b0 |
The monitor instance counts data transferred with any PMG value. |
| 0b1 |
The monitor instance only counts data transferred with the PMG value matching MSMON_CFG_MBWU_FLT.PMG. |
MATCH_PARTID, bit [16]
Match PARTID.
Controls whether the monitor instance counts only data transferred with PARTID matching MSMON_CFG_MBWU_FLT.PARTID.
| MATCH_PARTID | Meaning |
|---|---|
| 0b0 |
The monitor instance counts data transferred with any PARTID value. |
| 0b1 |
The monitor instance only counts data transferred with the PARTID value matching MSMON_CFG_MBWU_FLT.PARTID. |
OFLOW_STATUS_L, bit [15]
When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
Overflow Status of MSMON_MBWU_L.VALUE of the monitor instance.
Indicates whether MSMON_MBWU_L.VALUE has overflowed.
| OFLOW_STATUS_L | Meaning |
|---|---|
| 0b0 |
MSMON_MBWU_L.VALUE has not overflowed. |
| 0b1 |
MSMON_MBWU_L.VALUE has overflowed at least once since this bit was last written to zero. |
If MPAMF_MBWUMON_IDR.HAS_LONG == 0, this bit is RES0.
Overflow status of MSMON_MBWU.VALUE is reported in MSMON_CFG_MBWU_CTL.OFLOW_STATUS.
Otherwise:
Otherwise:
Reserved, RES0.
OFLOW_INTR_L, bit [14]
When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
Overflow Interrupt for MSMON_MBWU_L.
Controls whether an MPAM overflow interrupt is generated when MSMON_MBWU_L.VALUE overflows.
| OFLOW_INTR_L | Meaning |
|---|---|
| 0b0 |
No interrupt is signaled on an overflow of MSMON_MBWU_L.VALUE. |
| 0b1 |
An implementation-specific interrupt is signalled on overflow of MSMON_MBWU_L.VALUE. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
If the overflow interrupt is not supported by the MSC implementation, this field is RAZ/WI.
If MPAMF_MBWUMON_IDR.HAS_LONG == 0, this bit is RES0.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [13:8]
Reserved, RES0.
TYPE, bits [7:0]
Monitor Type Code. The MBWU monitor is TYPE = 0x42.
TYPE is a read-only constant indicating the type of the monitor.
Reads as 0x42.
Accessing the MSMON_CFG_MBWU_CTL
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MSMON_CFG_MBWU_CTL_s must be accessible from the Secure MPAM feature page. MSMON_CFG_MBWU_CTL_ns must be accessible from the Non-secure MPAM feature page.
MSMON_CFG_MBWU_CTL_s and MSMON_CFG_MBWU_CTL_ns must be separate registers. The Secure instance (MSMON_CFG_MBWU_CTL_s) accesses the memory bandwidth usage monitor controls used for Secure PARTIDs, and the Non-secure instance (MSMON_CFG_MBWU_CTL_ns) accesses the memory bandwidth usage monitor controls used for Non-secure PARTIDs.
When RIS is implemented, loads and stores to MSMON_CFG_MBWU_CTL access the monitor configuration settings for the bandwidth resource instance selected by MSMON_CFG_MON_SEL.RIS and the memory bandwidth usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
When RIS is not implemented, loads and stores to MSMON_CFG_MBWU_CTL access the monitor configuration settings for the memory bandwidth usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
MSMON_CFG_MBWU_CTL can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| MPAM | MPAMF_BASE_s | 0x0828 | MSMON_CFG_MBWU_CTL_s |
Accesses on this interface are RW.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| MPAM | MPAMF_BASE_ns | 0x0828 | MSMON_CFG_MBWU_CTL_ns |
Accesses on this interface are RW.