PMCEID0, Performance Monitors Common Event Identification register 0
The PMCEID0 characteristics are:
Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the range 0x0000 to 0x001F
When the value of a bit in the register is 1 the corresponding common event is implemented and counted.
For more information about the common events and the use of the PMCEIDn registers, see 'The PMU event number space and common events'.
- Arm recommends that, if a common event is never counted, the value of the corresponding register bit is 0.
- This view of the register was previously called PMCEID0_EL0.
External register PMCEID0 bits [31:0] are architecturally mapped to AArch64 System register PMCEID0_EL0[31:0] .
External register PMCEID0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0[31:0] .
PMCEID0 is in the Core power domain.
PMCEID0 is a 32-bit register.
The PMCEID0 bit assignments are:
ID<n>, bit [n], for n = 0 to 31
ID[n] corresponds to common event n.
For each bit:
The common event is not implemented, or not counted.
The common event is implemented.
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture.
Accessing the PMCEID0
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
PMCEID0 can be accessed through the external debug interface:
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and AllowExternalPMUAccess() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.