PMSWINC_EL0, Performance Monitors Software Increment register
The PMSWINC_EL0 characteristics are:
Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see SW_INCR.
External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMSWINC_EL0[31:0] .
External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMSWINC[31:0] .
PMSWINC_EL0 is in the Core power domain.
Implementation of this register is OPTIONAL.
If this register is implemented, use of it is deprecated.
If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface.
PMSWINC_EL0 is a 32-bit register.
The PMSWINC_EL0 bit assignments are:
P<n>, bit [n], for n = 0 to 30
Event counter software increment bit for PMEVCNTR<n>_EL0.
No action. The write to this bit is ignored.
It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter n.
Accessing the PMSWINC_EL0
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
PMSWINC_EL0 can be accessed through the external debug interface:
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and SoftwareLockStatus() accesses to this register are WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and !SoftwareLockStatus() accesses to this register are WO.
- Otherwise accesses to this register generate an error response.