TRCCIDR0, Component Identification Register 0
The TRCCIDR0 characteristics are:
Provides discovery information about the component.
For additional information see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCCIDR0 are RES0.
TRCCIDR0 is a 32-bit register.
The TRCCIDR0 bit assignments are:
PRMBL_0, bits [7:0]
Component identification preamble, segment 0.
Reads as 0x0D.
Accessing the TRCCIDR0
External debugger accesses to this register are unaffected by the OS Lock.
TRCCIDR0 can be accessed through the external debug interface:
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.