TRCCIDR1, Component Identification Register 1
The TRCCIDR1 characteristics are:
Provides discovery information about the component.
For additional information see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCCIDR1 are RES0.
TRCCIDR1 is a 32-bit register.
The TRCCIDR1 bit assignments are:
CLASS, bits [7:4]
Other values are defined by the CoreSight Architecture.
This field reads as 0x9.
PRMBL_1, bits [3:0]
Component identification preamble, segment 1.
Reads as 0b0000.
Accessing the TRCCIDR1
External debugger accesses to this register are unaffected by the OS Lock.
TRCCIDR1 can be accessed through the external debug interface:
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.