TRCPDSR, PowerDown Status Register
The TRCPDSR characteristics are:
Purpose
Indicates the power status of the trace unit.
Configuration
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCPDSR are RES0.
Attributes
TRCPDSR is a 32-bit register.
Field descriptions
The TRCPDSR bit assignments are:
Bits [31:6]
Reserved, RES0.
OSLK, bit [5]
OS Lock Status.
| OSLK | Meaning |
|---|---|
| 0b0 |
The OS Lock is unlocked. |
| 0b1 |
The OS Lock is locked. |
Note that this field indicates the state of the PE OS Lock.
Bits [4:2]
Reserved, RES0.
STICKYPD, bit [1]
Sticky powerdown status. Indicates whether the trace register state is valid.
| STICKYPD | Meaning |
|---|---|
| 0b0 |
The state of TRCOSLSR and the trace registers are valid. |
| 0b1 |
The state of TRCOSLSR and the trace registers might not be valid. |
This field is set to 0b1 if the power to the trace unit core power domain is removed and the trace unit register state is not valid.
The STICKYPD field is read-sensitive. On a read of the TRCPDSR, this field is cleared to 0b0 after the register has been read.
On a Trace unit reset, this field resets to 1.
POWER, bit [0]
Power Status.
| POWER | Meaning |
|---|---|
| 0b0 |
The trace unit core power domain is not powered. All trace unit registers are not accessible and they all return an error response. |
| 0b1 |
The trace unit core power domain is powered. Trace unit registers are accessible. |
Access to this field is RAO.
Accessing the TRCPDSR
External debugger accesses to this register are unaffected by the OS Lock.
TRCPDSR can be accessed through the external debug interface:
| Component | Offset |
|---|---|
| ETE | 0x314 |
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.