TRCPIDR5, Peripheral Identification Register 5
The TRCPIDR5 characteristics are:
Provides discovery information about the component.
For additional information see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCPIDR5 are RES0.
TRCPIDR5 is a 32-bit register.
The TRCPIDR5 bit assignments are:
Accessing the TRCPIDR5
External debugger accesses to this register are unaffected by the OS Lock.
TRCPIDR5 can be accessed through the external debug interface:
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.