AMCFGR_EL0, Activity Monitors Configuration Register
The AMCFGR_EL0 characteristics are:
Purpose
Global configuration register for the activity monitors.
Provides information on supported features, the number of counter groups implemented, the total number of activity monitor event counters implemented, and the size of the counters. AMCFGR_EL0 is applicable to both the architected and the auxiliary counter groups.
Configuration
AArch64 System register AMCFGR_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMCFGR[31:0] .
AArch64 System register AMCFGR_EL0 bits [31:0] are architecturally mapped to External register AMCFGR[31:0] .
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCFGR_EL0 are UNDEFINED.
Attributes
AMCFGR_EL0 is a 64-bit register.
Field descriptions
The AMCFGR_EL0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| NCG | RES0 | HDBG | RAZ | SIZE | N | ||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
NCG, bits [31:28]
Defines the number of counter groups.
The number of implemented counter groups is defined as [AMCFGR_EL0.NCG + 1].
If the number of implemented auxiliary activity monitor event counters is zero, this field has a value of 0b0000. Otherwise, this field has a value of 0b0001.
Bits [27:25]
Reserved, RES0.
HDBG, bit [24]
Halt-on-debug supported.
From Armv8, this feature must be supported, and so this bit is 0b1.
| HDBG | Meaning |
|---|---|
| 0b0 |
AMCR_EL0.HDBG is RES0. |
| 0b1 |
AMCR_EL0.HDBG is read/write. |
Bits [23:14]
Reserved, RAZ.
SIZE, bits [13:8]
Defines the size of activity monitor event counters.
The size of the activity monitor event counters implemented by the activity monitors Extension is defined as [AMCFGR_EL0.SIZE + 1].
From Armv8, the counters are 64-bit, and so this field is 0b111111.
Software also uses this field to determine the spacing of counters in the memory-map. From Armv8, the counters are at doubleword-aligned addresses.
N, bits [7:0]
Defines the number of activity monitor event counters.
The total number of counters implemented in all groups by the Activity Monitors Extension is defined as [AMCFGR_EL0.N + 1].
Accessing the AMCFGR_EL0
Accesses to this register use the following encodings:
MRS <Xt>, AMCFGR_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCFGR_EL0;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif EL2Enabled() && CPTR_EL2.TAM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCFGR_EL0;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return AMCFGR_EL0;
elsif PSTATE.EL == EL3 then
return AMCFGR_EL0;