BRBCR_EL2, Branch Record Buffer Control Register (EL2)
The BRBCR_EL2 characteristics are:
Purpose
Controls the Branch Record Buffer.
Configuration
This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBCR_EL2 are UNDEFINED.
Attributes
BRBCR_EL2 is a 64-bit register.
Field descriptions
The BRBCR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | EXCEPTION | ERTN | RES0 | FZP | RES0 | TS | MPRED | CC | RES0 | E2BRE | E0HBRE | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:24]
Reserved, RES0.
EXCEPTION, bit [23]
Enable the recording of entry to EL2 via an exception.
EXCEPTION | Meaning |
---|---|
0b0 |
Disable the recording of Branch records for exceptions when taken to EL2. |
0b1 |
Enable the recording of Branch records for exceptions when taken to EL2. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
ERTN, bit [22]
Allow the recording Branch records for exception return instructions from EL2.
ERTN | Meaning |
---|---|
0b0 |
Disable the recording Branch records for exception return instructions from EL2. |
0b1 |
Enable the recording Branch records for exception return instructions from EL2. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [21:9]
Reserved, RES0.
FZP, bit [8]
When FEAT_PMUv3 is implemented:
When FEAT_PMUv3 is implemented:
Freeze BRBE on PMU overflow.
FZP | Meaning |
---|---|
0b0 |
Branch recording is not affected by this control. |
0b1 |
A BRBE freeze event occurs when a PMU overflow occurs. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [7]
Reserved, RES0.
TS, bits [6:5]
Timestamp Control.
TS | Meaning | Applies when |
---|---|---|
0b00 |
Timestamp controlled by BRBCR_EL1.TS. | |
0b01 |
Virtual timestamp. The BRBE recorded timestamp is the physical counter value, minus the value of CNTVOFF_EL2. | |
0b10 | Guest physical timestamp. The BRBE recorded timestamp is the physical counter value minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:
| When FEAT_ECV is implemented |
0b11 |
Physical timestamp. The BRBE recorded timestamp is the physical counter value. |
On a Warm reset, this field resets to 0.
MPRED, bit [4]
Mask the recording of mispredicts.
MPRED | Meaning |
---|---|
0b0 |
Disable the recording of mispredict information. |
0b1 |
Allow the recording of mispredict information. |
If EL2 is not implemented or EL2 is disabled in the current Security state, then the Effective value of this bit is 0b1, other than for a direct read of the register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
CC, bit [3]
Enable the recording of cycle count information.
CC | Meaning |
---|---|
0b0 |
Disable the recording of cycle count information. |
0b1 |
Allow the recording of cycle count information. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [2]
Reserved, RES0.
E2BRE, bit [1]
EL2 Branch recording enable.
E2BRE | Meaning |
---|---|
0b0 |
Branch recording prohibited at EL2. |
0b1 |
Branch recording enabled at EL2. |
On a Warm reset, this field resets to 0.
E0HBRE, bit [0]
EL0 Branch recording enable.
E0HBRE | Meaning |
---|---|
0b0 |
Branch recording prohibited at EL0 when HCR_EL2.TGE == 0b1. |
0b1 |
Branch recording enabled at EL0 when HCR_EL2.TGE == 0b1. |
This bit is ignored by the PE when any of the following are true:
- HCR_EL2.TGE == 0b0.
- EL2 is disabled in the current Security state.
On a Warm reset, this field resets to 0.
Accessing the BRBCR_EL2
Accesses to this register use the following encodings:
MRS <Xt>, BRBCR_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b1001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGRTR_EL2.nBRBCTL == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x8E0]; else return BRBCR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return BRBCR_EL2; else return BRBCR_EL1; elsif PSTATE.EL == EL3 then return BRBCR_EL1;
MRS <Xt>, BRBCR_EL2
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b100 | 0b1001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return BRBCR_EL2; elsif PSTATE.EL == EL3 then return BRBCR_EL2;
MSR BRBCR_EL1, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b1001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGWTR_EL2.nBRBCTL == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x8E0] = X[t]; else BRBCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then BRBCR_EL2 = X[t]; else BRBCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then BRBCR_EL1 = X[t];
MSR BRBCR_EL2, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b100 | 0b1001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else BRBCR_EL2 = X[t]; elsif PSTATE.EL == EL3 then BRBCR_EL2 = X[t];