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BRBINFINJ_EL1, Branch Record Buffer Information Injection Register

The BRBINFINJ_EL1 characteristics are:

Purpose

The information of a Branch record for injection.

Configuration

This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBINFINJ_EL1 are UNDEFINED.

Attributes

BRBINFINJ_EL1 is a 64-bit register.

Field descriptions

The BRBINFINJ_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0CCUCC
RES0LASTFAILEDTRES0TYPEELMPREDRES0VALID
313029282726252423222120191817161514131211109876543210

Bits [63:47]

Reserved, RES0.

CCU, bit [46]

The number of PE clock cycles since the last Branch record entry is UNKNOWN.

CCUMeaning
0b0

Indicates that the number of PE clock cycles since the last Branch record is indicated by BRBINFINJ_EL1.CC.

0b1

Indicates that the number of PE clock cycles since the last Branch record is UNKNOWN.

The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.

This bit is RES0 if BRBINFINJ_EL1.VALID == 0b00.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CC, bits [45:32]

The number of PE clock cycles since the last Branch record entry.

The format of this field uses a mantissa and exponent to express the cycle count value.

CC bits[7:0] indicate the mantissa M.

CC bits[13:8] indicate the exponent E.

The cycle count is expressed using the following function:

cycle_count = IsZero(E) ? UInt(M) : UInt('1':M:Zeros(UInt(E)-1))

A value of all ones in both the mantissa and exponent indicates the cycle count value exceeded the size of the cycle counter.

The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.

This field is RES0 if any of the following are true:

  • BRBINFINJ_EL1.CCU == 0b1.
  • BRBINFINJ_EL1.VALID == 0b00.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [31:18]

Reserved, RES0.

LASTFAILED, bit [17]

When FEAT_TME is implemented:

The last transaction failed.

LASTFAILEDMeaning
0b0

Indicates that a transaction did not fail between the previous Branch record and this Branch record.

0b1

Indicates that a transaction failed between the previous Branch record and this Branch record.

The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.

This bit is RES0 if BRBINFINJ_EL1.VALID == 0b00.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

T, bit [16]

When FEAT_TME is implemented:

Transactional state.

TMeaning
0b0

The branch or exception was not executed in Transactional state.

0b1

The branch or exception was executed in Transactional state.

The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b10 or BRBINFINJ_EL1.VALID == 0b11.

This bit is RES0 if any of the following are true:

  • BRBINFINJ_EL1.VALID == 0b00.
  • BRBINFINJ_EL1.VALID == 0b01.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [15:14]

Reserved, RES0.

TYPE, bits [13:8]

Branch type.

TYPEMeaning
0b000000

Direct branch, excluding Branch with link.

0b000001

Indirect branch, excluding Branch with link, Return from subroutine, and Exception return.

0b000010

Direct Branch with link.

0b000011

Indirect Branch with link.

0b000101

Return from subroutine.

0b000111

Exception return.

0b100001

Debug halt.

0b100010

Call.

0b100011

Trap.

0b100100

SError.

0b100110

Instruction debug.

0b100111

Data debug.

0b101010

Alignment.

0b101011

Inst Fault.

0b101100

Data Fault.

0b101110

IRQ.

0b101111

FIQ.

0b111001

Debug State Exit.

All other values are reserved.

The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.

This field is RES0 if BRBINFINJ_EL1.VALID == 0b00.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

EL, bits [7:6]

The Exception Level at the target address.

ELMeaning
0b00

EL0.

0b01

EL1.

0b10

EL2.

All other values are reserved.

The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b11 or BRBINFINJ_EL1.VALID == 0b01.

This field is RES0 if any of the following are true:

  • BRBINFINJ_EL1.VALID == 0b00.
  • BRBINFINJ_EL1.VALID == 0b10.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

MPRED, bit [5]

Branch mispredict.

MPREDMeaning
0b0

Branch was correctly predicted or the result of the prediction was not captured.

0b1

Branch was incorrectly predicted.

The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b11 or BRBINFINJ_EL1.VALID == 0b10.

This bit is RES0 if any of the following are true:

  • BRBINFINJ_EL1.VALID == 0b00.
  • BRBINFINJ_EL1.VALID == 0b01.
  • BRBINFINJ_EL1.TYPE[5] == 0b1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [4:2]

Reserved, RES0.

VALID, bits [1:0]

The Branch record is valid.

VALIDMeaning
0b00

This Branch record is not valid.

The values of following fields are not valid:

  • BRBTGTINJ_EL1.ADDRESS.
  • BRBSRCINJ_EL1.ADDRESS.
  • BRBINFINJ_EL1.LASTFAILED.
  • BRBINFINJ_EL1.T.
  • BRBINFINJ_EL1.EL.
  • BRBINFINJ_EL1.TYPE.
  • BRBINFINJ_EL1.CC.
  • BRBINFINJ_EL1.CCU.
0b01

This Branch record is valid.

The values of following fields are not valid:

0b10

This Branch record is valid.

The values of following fields are not valid:

0b11

This Branch record is valid.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the BRBINFINJ_EL1

Accesses to this register use the following encodings:

MRS <Xt>, BRBINFINJ_EL1

op0op1CRnCRmop2
0b100b0010b10010b00010b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGRTR_EL2.nBRBDATA == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return BRBINFINJ_EL1;
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return BRBINFINJ_EL1;
elsif PSTATE.EL == EL3 then
    return BRBINFINJ_EL1;
              

MSR BRBINFINJ_EL1, <Xt>

op0op1CRnCRmop2
0b100b0010b10010b00010b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGWTR_EL2.nBRBDATA == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        BRBINFINJ_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        BRBINFINJ_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    BRBINFINJ_EL1 = X[t];