BRBINF<n>_EL1, Branch Record Buffer Information Register <n>, n = 0 - 31

The BRBINF<n>_EL1 characteristics are:

Purpose

The information for Branch record n + (BRBFCR_EL1.BANK × 32).

Configuration

This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBINF<n>_EL1 are UNDEFINED.

Attributes

BRBINF<n>_EL1 is a 64-bit register.

Field descriptions

The BRBINF<n>_EL1 bit assignments are:

Bits [63:47]

Reserved, RES0.

CCU, bit [46]

The number of PE clock cycles since the last Branch record entry is UNKNOWN.

The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00.

This bit is RES0 if BRBINF<n>_EL1.VALID == 0b00.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

CC, bits [45:32]

The number of PE clock cycles since the last Branch record entry.

The format of this field uses a mantissa and exponent to express the cycle count value.

CC bits[7:0] indicate the mantissa M.

CC bits[13:8] indicate the exponent E.

The cycle count is expressed using the following function:

cycle_count = IsZero(E) ? UInt(M) : UInt('1':M:Zeros(UInt(E)-1))

A value of all ones in both the mantissa and exponent indicates the cycle count value exceeded the size of the cycle counter.

The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00.

This field is RES0 if any of the following are true:

• BRBINF<n>_EL1.CCU == 0b1.
• BRBINF<n>_EL1.VALID == 0b00.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [31:18]

Reserved, RES0.

LASTFAILED, bit [17]

When FEAT_TME is implemented:

The last transaction failed.

The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00.

This bit is RES0 if BRBINF<n>_EL1.VALID == 0b00.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Reserved, RES0.

T, bit [16]

When FEAT_TME is implemented:

Transactional state.

The value in this field is only valid when BRBINF<n>_EL1.VALID == 0b10 or BRBINF<n>_EL1.VALID == 0b11.

This bit is RES0 if any of the following are true:

• BRBINF<n>_EL1.VALID == 0b00.
• BRBINF<n>_EL1.VALID == 0b01.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Reserved, RES0.

Bits [15:14]

Reserved, RES0.

TYPE, bits [13:8]

Branch type.

All other values are reserved.

The value in this field is only valid when BRBINF<n>_EL1.VALID != 0b00.

This field is RES0 if BRBINF<n>_EL1.VALID == 0b00.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

EL, bits [7:6]

The Exception Level at the target address.

All other values are reserved.

The value in this field is only valid when BRBINF<n>_EL1.VALID == 0b11 or BRBINF<n>_EL1.VALID == 0b01.

This field is RES0 if any of the following are true:

• BRBINF<n>_EL1.VALID == 0b00.
• BRBINF<n>_EL1.VALID == 0b10.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

MPRED, bit [5]

Branch mispredict.

The value in this field is only valid when BRBINF<n>_EL1.VALID == 0b11 or BRBINF<n>_EL1.VALID == 0b10.

This bit is RES0 if any of the following are true:

• BRBINF<n>_EL1.VALID == 0b00.
• BRBINF<n>_EL1.VALID == 0b01.
• BRBINF<n>_EL1.TYPE[5] == 0b1.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [4:2]

Reserved, RES0.

VALID, bits [1:0]

The Branch record is valid.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGRTR_EL2.nBRBDATA == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return BRBINF_EL1[UInt(op2<2>:CRm<3:0>)];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        UNDEFINED;
    elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return BRBINF_EL1[UInt(op2<2>:CRm<3:0>)];
elsif PSTATE.EL == EL3 then
    return BRBINF_EL1[UInt(op2<2>:CRm<3:0>)];