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CSR, Call Stack Recording

The CSR characteristics are:

Purpose

Allows access to the Call Stack Recording bit.

Configuration

This register is present only when FEAT_CSRE is implemented. Otherwise, direct accesses to CSR are UNDEFINED.

Attributes

CSR is a 64-bit register.

Field descriptions

The CSR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0CSR
RES0
313029282726252423222120191817161514131211109876543210

Bits [63:33]

Reserved, RES0.

CSR, bit [32]

Call Stack Recording.

CSRMeaning
0b0

Causes call stack recording to be paused

0b1

Does not cause call stack recording to be paused

Note

In MSR CSR, #<imm> variant, bits CRm[3:1] are not ignored and must be 0b000. CRm[0] encodes the immediate value.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [31:0]

Reserved, RES0.

Accessing the CSR

Accesses to this register use the following encodings:

MRS <Xt>, CSR

op0op1CRnCRmop2
0b110b0110b01000b00100b100
if PSTATE.EL == EL0 then
    return Zeros(31):PSTATE.CSR:Zeros(32);
elsif PSTATE.EL == EL1 then
    return Zeros(31):PSTATE.CSR:Zeros(32);
elsif PSTATE.EL == EL2 then
    return Zeros(31):PSTATE.CSR:Zeros(32);
elsif PSTATE.EL == EL3 then
    return Zeros(31):PSTATE.CSR:Zeros(32);
              

MSR CSR, <Xt>

op0op1CRnCRmop2
0b110b0110b01000b00100b100
if PSTATE.EL == EL0 then
    PSTATE.CSR = X[t]<32>;
elsif PSTATE.EL == EL1 then
    PSTATE.CSR = X[t]<32>;
elsif PSTATE.EL == EL2 then
    PSTATE.CSR = X[t]<32>;
elsif PSTATE.EL == EL3 then
    PSTATE.CSR = X[t]<32>;
              

MSR CSR, #<imm>

op0op1CRnCRmop2
0b000b0110b01000b000x0b011