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CSRCR_EL0, Call Stack Recorder Control (EL0)

The CSRCR_EL0 characteristics are:

Purpose

Controls the Call Stack Recorder at EL0.

Configuration

This register is present only when FEAT_CSRE is implemented. Otherwise, direct accesses to CSRCR_EL0 are UNDEFINED.

Attributes

CSRCR_EL0 is a 64-bit register.

Field descriptions

The CSRCR_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PANSIZENPUFOFEN
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Reserved, RES0.

PAN, bit [10]

Call Stack Recorder Privilege Access Never.

When the first stage of translation is disabled for the current translation regime, the Effective value of this bit is 0b0.

When the first stage of translation for the current translation regime does not describe the permissions for access at EL0, the Effective value of this bit is 0b0.

PANMeaning
0b0

This field has no effect on stores performed by the Call Stack Recorder at EL0.

0b1

Privileged accesses by the Call Stack Recorder at EL0 generate a Permission fault if EL0 has data or instruction access permissions to the access address.

This bit is permitted to be cached in a TLB.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When accessed from EL0, access to this field is RAZ/WI.

SIZE, bits [9:4]

Size of the Call Stack Recorder buffer at EL0.

SIZEMeaning
0b001001

Buffer is 512 bytes.

0b001010

Buffer is 1KB.

0b001011

Buffer is 2KB.

0b001100

Buffer is 4KB.

0b001110

Buffer is 16KB.

0b010000

Buffer is 64KB.

0b010101

Buffer is 2MB.

All other values are reserved.

If this field is programmed with a reserved value then the PE treats the field as if it has been programmed with a CONSTRAINED UNPREDICTABLE choice of one of the valid values, for all purposes other than the value read back from the register.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

NP, bit [3]

Call Stack Recorder privilege.

Controls whether EL0 Call Stack Recorder stores are privileged or unprivileged.

When the first stage of translation is disabled for the current translation regime, the Effective value of this bit is 0b1.

When EL2 is not implemented or not enabled for the current Security state, and SCTLR_EL1.EnCSR0 == 0b11, the Effective value of this bit is 0b1.

When EL2 is implemented and enabled for the current Security state, and HCR_EL2.{E2H,TGE} != {1,1}, and SCTLR_EL1.EnCSR0 == 0b11, the Effective value of this bit is 0b1.

When EL2 is implemented and enabled for the current Security state, and HCR_EL2.{E2H,TGE} == {1,1}, and SCTLR_EL2.EnCSR0 == 0b11, the Effective value of this bit is 0b1.

NPMeaning
0b0

Call Stack Recording stores at EL0 are privileged.

0b1

Call Stack Recording stores at EL0 are unprivileged.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When accessed from EL0, access to this field is RAO/WI.

UF, bit [2]

Call Stack Recording Underflow.

UFMeaning
0b0

Call Stack Recording at EL0 has not Underflowed.

0b1

Call Stack Recording at EL0 has Underflowed.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

OF, bit [1]

Call Stack Recording Overflow.

OFMeaning
0b0

Call Stack Recording at EL0 has not Overflowed.

0b1

Call Stack Recording at EL0 has Overflowed.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

EN, bit [0]

Call Stack Recording Enable.

ENMeaning
0b0

Call Stack Recording disabled at EL0.

0b1

Call Stack Recording enabled at EL0.

On a Warm reset, this field resets to 0.

Accessing the CSRCR_EL0

Accesses to this register use the following encodings:

MRS <Xt>, CSRCR_EL0

op0op1CRnCRmop2
0b100b0110b10000b00000b000
if PSTATE.EL == EL0 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif (!EL2Enabled() || HCR_EL2.<E2H,TGE> != '11') && SCTLR_EL1.EnCSR0 == '00' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.EnCSR0 == '00' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRCR_EL0;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRCR_EL0;
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRCR_EL0;
elsif PSTATE.EL == EL3 then
    return CSRCR_EL0;
              

MSR CSRCR_EL0, <Xt>

op0op1CRnCRmop2
0b100b0110b10000b00000b000
if PSTATE.EL == EL0 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif (!EL2Enabled() || HCR_EL2.<E2H,TGE> != '11') && SCTLR_EL1.EnCSR0 == '0x' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.EnCSR0 == '0x' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGWTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        CSRCR_EL0 = X[t];
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGWTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        CSRCR_EL0 = X[t];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        CSRCR_EL0 = X[t];
elsif PSTATE.EL == EL3 then
    CSRCR_EL0 = X[t];