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CSRCR_EL1, Call Stack Recorder Control (EL1)

The CSRCR_EL1 characteristics are:

Purpose

Controls the Call Stack Recorder at EL1.

Configuration

This register is present only when FEAT_CSRE is implemented. Otherwise, direct accesses to CSRCR_EL1 are UNDEFINED.

Attributes

CSRCR_EL1 is a 64-bit register.

Field descriptions

The CSRCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PANSIZERES0UFOFEN
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Reserved, RES0.

PAN, bit [10]

Call Stack Recorder Privilege Access Never.

When the first stage of translation is disabled for the current translation regime, the Effective value of this bit is 0b0.

When the first stage of translation for the current translation regime does not describe the permissions for access at EL0, the Effective value of this bit is 0b0.

PANMeaning
0b0

This field has no effect on stores performed by the Call Stack Recorder at EL1.

0b1

Privileged accesses by the Call Stack Recorder at EL1 generate a Permission fault if EL0 has data or instruction access permissions to the access address.

This bit is permitted to be cached in a TLB.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

SIZE, bits [9:4]

Size of the Call Stack Recorder buffer at EL1.

SIZEMeaning
0b001001

Buffer is 512 bytes.

0b001010

Buffer is 1KB.

0b001011

Buffer is 2KB.

0b001100

Buffer is 4KB.

0b001110

Buffer is 16KB.

0b010000

Buffer is 64KB.

0b010101

Buffer is 2MB.

All other values are reserved.

If this field is programmed with a reserved value then the PE treats the field as if it has been programmed with a CONSTRAINED UNPREDICTABLE choice of one of the valid values, for all purposes other than the value read back from the register.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [3]

Reserved, RES0.

UF, bit [2]

Call Stack Recording Underflow.

UFMeaning
0b0

Call Stack Recording at EL1 has not Underflowed.

0b1

Call Stack Recording at EL1 has Underflowed.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

OF, bit [1]

Call Stack Recording Overflow.

OFMeaning
0b0

Call Stack Recording at EL1 has not Overflowed.

0b1

Call Stack Recording at EL1 has Overflowed.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

EN, bit [0]

Call Stack Recording Enable.

ENMeaning
0b0

Call Stack Recording disabled at EL1.

0b1

Call Stack Recording enabled at EL1.

On a Warm reset, this field resets to 0.

Accessing the CSRCR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, CSRCR_EL1

op0op1CRnCRmop2
0b100b0000b10000b00000b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL1 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
        return NVMem[0x8D0];
    else
        return CSRCR_EL1;
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        return CSRCR_EL2;
    else
        return CSRCR_EL1;
elsif PSTATE.EL == EL3 then
    return CSRCR_EL1;
              

MRS <Xt>, CSRCR_EL12

op0op1CRnCRmop2
0b100b1010b10000b00000b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
        return NVMem[0x8D0];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
            UNDEFINED;
        elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
            if Halted() && EDSCR.SDD == '1' then
                UNDEFINED;
            else
                AArch64.SystemAccessTrap(EL3, 0x18);
        else
            return CSRCR_EL1;
    else
        UNDEFINED;
elsif PSTATE.EL == EL3 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then
        return CSRCR_EL1;
    else
        UNDEFINED;
              

MSR CSRCR_EL1, <Xt>

op0op1CRnCRmop2
0b100b0000b10000b00000b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGWTR_EL2.nCSR_EL1 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
        NVMem[0x8D0] = X[t];
    else
        CSRCR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        CSRCR_EL2 = X[t];
    else
        CSRCR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    CSRCR_EL1 = X[t];
              

MSR CSRCR_EL12, <Xt>

op0op1CRnCRmop2
0b100b1010b10000b00000b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
        NVMem[0x8D0] = X[t];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
            UNDEFINED;
        elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
            if Halted() && EDSCR.SDD == '1' then
                UNDEFINED;
            else
                AArch64.SystemAccessTrap(EL3, 0x18);
        else
            CSRCR_EL1 = X[t];
    else
        UNDEFINED;
elsif PSTATE.EL == EL3 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then
        CSRCR_EL1 = X[t];
    else
        UNDEFINED;