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CSRPTRIDX_EL0, Call Stack Recorder Pointer Index (EL0)

The CSRPTRIDX_EL0 characteristics are:

Purpose

Contains the Call stack pointer index at EL0.

Configuration

This register is present only when FEAT_CSRE is implemented. Otherwise, direct accesses to CSRPTRIDX_EL0 are UNDEFINED.

Attributes

CSRPTRIDX_EL0 is a 64-bit register.

Field descriptions

The CSRPTRIDX_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PTRRES0
313029282726252423222120191817161514131211109876543210

Bits [63:21]

Reserved, RES0.

PTR, bits [20:3]

EL0 Call stack pointer index.

The number of valid bits in PTR is defined by the currently selected size of the Call Stack Record Buffer, and controlled by CSRCR_EL0.SIZE. The currently selected size defines a number S which is the index of the most significant valid bit of CSRPTRIDX_EL0.

PTR contains bits [S:3] of the virtual address of the next entry to be written in the Call Stack Recorder buffer.

Bits [2:0] of the virtual address are always zero.

When S is less than 20, CSRPTRIDX_EL0[20:S+1] return a value of zero.

CSRPTRIDX_EL0[S:3] are mapped to CSRPTR_EL0[S:3].

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [2:0]

Reserved, RES0.

Accessing the CSRPTRIDX_EL0

Accesses to this register use the following encodings:

MRS <Xt>, CSRPTRIDX_EL0

op0op1CRnCRmop2
0b100b0110b10000b00000b011
if PSTATE.EL == EL0 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif (!EL2Enabled() || HCR_EL2.<E2H,TGE> != '11') && SCTLR_EL1.EnCSR0 == '00' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.EnCSR0 == '00' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRPTRIDX_EL0;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL0 == '0') then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRPTRIDX_EL0;
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return CSRPTRIDX_EL0;
elsif PSTATE.EL == EL3 then
    return CSRPTRIDX_EL0;