CSRPTRIDX_EL1, Call Stack Recorder Pointer Index (EL1)
The CSRPTRIDX_EL1 characteristics are:
Purpose
Contains the Call stack pointer index at EL1.
Configuration
This register is present only when FEAT_CSRE is implemented. Otherwise, direct accesses to CSRPTRIDX_EL1 are UNDEFINED.
Attributes
CSRPTRIDX_EL1 is a 64-bit register.
Field descriptions
The CSRPTRIDX_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | PTR | RES0 | |||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:21]
Reserved, RES0.
PTR, bits [20:3]
EL1 Call stack pointer index.
The number of valid bits in PTR is defined by the currently selected size of the Call Stack Record Buffer, and controlled by CSRCR_EL1.SIZE. The currently selected size defines a number S which is the index of the most significant valid bit of CSRPTRIDX_EL1.
PTR contains bits [S:3] of the virtual address of the next entry to be written in the Call Stack Recorder buffer.
Bits [2:0] of the virtual address are always zero.
When S is less than 20, CSRPTRIDX_EL1[20:S+1] return a value of zero.
CSRPTRIDX_EL1[S:3] are mapped to CSRPTR_EL1[S:3].
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [2:0]
Reserved, RES0.
Accessing the CSRPTRIDX_EL1
Accesses to this register use the following encodings:
MRS <Xt>, CSRPTRIDX_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b000 | 0b1000 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
UNDEFINED;
elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HFGRTR_EL2.nCSR_EL1 == '0') then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return CSRPTRIDX_EL1;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.EnCSR == '0' then
UNDEFINED;
elsif HaveEL(EL3) && SCR_EL3.EnCSR == '0' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HCR_EL2.E2H == '1' then
return CSRPTRIDX_EL2;
else
return CSRPTRIDX_EL1;
elsif PSTATE.EL == EL3 then
return CSRPTRIDX_EL1;