HPFAR_EL2, Hypervisor IPA Fault Address Register
The HPFAR_EL2 characteristics are:
Purpose
Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.
Configuration
AArch64 System register HPFAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HPFAR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
The HPFAR_EL2 is written for:
- Translation or Access faults in the second stage of translation.
- An abort in the second stage of translation performed during the translation table walk of a first stage translation, caused by a Translation fault, an Access flag fault, or a Permission fault.
- A stage 2 Address size fault.
For all other exceptions taken to EL2, this register is UNKNOWN.
The address held in this register is an address accessed by the instruction fetch or data access that caused the exception that gave rise to the instruction or data abort. It is the lowest address that gave rise to the fault. Where different faults from different addresses arise from the same instruction, such as for an instruction that loads or stores a mis-aligned address that crosses a page boundary, the architecture does not prioritize between those different faults.
Attributes
HPFAR_EL2 is a 64-bit register.
Field descriptions
The HPFAR_EL2 bit assignments are:
Execution at EL1 or EL0 makes HPFAR_EL2 become UNKNOWN.
NS, bit [63]
When FEAT_SEL2 is implemented:
When FEAT_SEL2 is implemented:
Faulting IPA address space.
| NS | Meaning |
|---|---|
| 0b0 |
Faulting IPA is from the Secure IPA space. |
| 0b1 |
Faulting IPA is from the Non-secure IPA space. |
For Data Aborts or Instruction Aborts taken to Non-secure EL2, this field is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [62:44]
Reserved, RES0.
FIPA, bits [43:4]
FIPA encoding when FEAT_LPA is implemented38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIPA
| 38 | 37 | 36 | 35 | 34 | 33 | 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIPA | ||||||||||||||||||||||||||||||||||||||
FIPA, bits [38:0]
Faulting Intermediate Physical Address.
When 52-bit addresses and a 64KB translation granule are in use for the stage 1 translation, HPFAR_EL2.FIPA[38:35] forms the upper part of the address value.
For implementations or stage 1 translation granules with fewer than 52 physical address bits the HPFAR_EL2.FIPA[38:35] is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
FIPA encoding when FEAT_LPA is not implemented
Bits [38:35]
Reserved, RES0.
FIPA, bits [34:0]
Faulting Intermediate Physical Address.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [3:0]
Reserved, RES0.
Accessing the HPFAR_EL2
Accesses to this register use the following encodings:
MRS <Xt>, HPFAR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return HPFAR_EL2;
elsif PSTATE.EL == EL3 then
return HPFAR_EL2;
MSR HPFAR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
HPFAR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
HPFAR_EL2 = X[t];