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ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1
The ID_AA64DFR1_EL1 characteristics are:
Purpose
Reserved for future expansion of top level information about the debug system in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Configuration
There are no configuration notes.
Attributes
ID_AA64DFR1_EL1 is a 64-bit register.
Field descriptions
The ID_AA64DFR1_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Reserved, RES0.
Accessing the ID_AA64DFR1_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_AA64DFR1_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then
if IsFeatureImplemented(FEAT_IDST) then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_AA64DFR1_EL1;
elsif PSTATE.EL == EL2 then
return ID_AA64DFR1_EL1;
elsif PSTATE.EL == EL3 then
return ID_AA64DFR1_EL1;