MPAM2_EL2, MPAM2 Register (EL2)
The MPAM2_EL2 characteristics are:
Purpose
Holds information to generate MPAM labels for memory requests when executing at EL2.
Configuration
AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register MPAM3_EL3[63] when EL3 is implemented.
AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register MPAM1_EL1[63] .
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAM2_EL2 are UNDEFINED.
This register has no effect if EL2 is not enabled in the current Security state.
Attributes
MPAM2_EL2 is a 64-bit register.
Field descriptions
The MPAM2_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| MPAMEN | RES0 | TIDR | RES0 | TRAPMPAM0EL1 | TRAPMPAM1EL1 | PMG_D | PMG_I | ||||||||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPAMEN, bit [63]
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information from all Exception levels. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. |
If EL3 is not implemented, this field is read/write.
If EL3 is implemented, this field is read-only and reads the current value of the read/write MPAM3_EL3.MPAMEN bit.
On a Warm reset, this field resets to 0.
Accessing this field has the following behavior:
- When EL3 is not implemented, access to this field is RW.
- Otherwise, access to this field is RO.
Bits [62:59]
Reserved, RES0.
TIDR, bit [58]
When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMIDR_EL1.HAS_TIDR == 1:
When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMIDR_EL1.HAS_TIDR == 1:
TIDR traps accesses to MPAMIDR_EL1 from EL1 to EL2.
| TIDR | Meaning |
|---|---|
| 0b0 |
This control does not cause any instructions to be trapped. |
| 0b1 |
Trap accesses to MPAMIDR_EL1 from EL1 to EL2. |
MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == 1 also traps MPAMIDR_EL1 accesses from EL1 to EL2. If either TIDR or TRAP_MPAMIDR_EL1 are 1, accesses are trapped.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [57:50]
Reserved, RES0.
TRAPMPAM0EL1, bit [49]
TRAPMPAM0EL1: Trap accesses from EL1 to the MPAM0_EL1 register trap to EL2.
| TRAPMPAM0EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAM0_EL1 from EL1 are not trapped. |
| 0b1 |
Accesses to MPAM0_EL1 from EL1 are trapped to EL2. |
On a Warm reset, when EL3 is not implemented, this field resets to 1.
On a Warm reset, when EL3 is implemented, this field resets to an architecturally UNKNOWN value.
TRAPMPAM1EL1, bit [48]
TRAPMPAM1EL1: Trap accesses from EL1 to the MPAM1_EL1 register trap to EL2.
| TRAPMPAM1EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAM1_EL1 from EL1 are not trapped. |
| 0b1 |
Accesses to MPAM1_EL1 from EL1 are trapped to EL2. |
On a Warm reset, when EL3 is not implemented, this field resets to 1.
On a Warm reset, when EL3 is implemented, this field resets to an architecturally UNKNOWN value.
PMG_D, bits [47:40]
Performance monitoring group for data accesses.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
PMG_I, bits [39:32]
Performance monitoring group for instruction accesses.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
PARTID_D, bits [31:16]
Partition ID for data accesses, including load and store accesses, made from EL2.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
PARTID_I, bits [15:0]
Partition ID for instruction accesses made from EL2.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the MPAM2_EL2
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings:
MRS <Xt>, MPAM2_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return MPAM2_EL2;
elsif PSTATE.EL == EL3 then
return MPAM2_EL2;
MSR MPAM2_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
MPAM2_EL2 = X[t];
elsif PSTATE.EL == EL3 then
MPAM2_EL2 = X[t];
MRS <Xt>, MPAM1_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM1EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
return NVMem[0x900];
else
return MPAM1_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HCR_EL2.E2H == '1' then
return MPAM2_EL2;
else
return MPAM1_EL1;
elsif PSTATE.EL == EL3 then
return MPAM1_EL1;
MSR MPAM1_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM1EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
NVMem[0x900] = X[t];
else
MPAM1_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HCR_EL2.E2H == '1' then
MPAM2_EL2 = X[t];
else
MPAM1_EL1 = X[t];
elsif PSTATE.EL == EL3 then
MPAM1_EL1 = X[t];